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Mapping irregular applications to DIVA, a PIM-based data-intensive architecture

Mary Hall, Apoorv Srivastava, William Athas, Vincent Freeh, Jaewook Shin, Joonseok Park, Peter Kogge, Jeff Koller, Pedro Diniz, Jacqueline Chame, Jeff Draper, Jeff LaCoss (+2 others)
1999 Proceedings of the 1999 ACM/IEEE conference on Supercomputing (CDROM) - Supercomputing '99  
The Data-IntensiVe Architecture (DIVA) system combines PIM memories with one or more external host processors and a PIM-to-PIM interconnect.  ...  DIVA uniquely supports acceleration of important irregular applications, including sparse-matrix and pointer-based computations.  ...  Acknowledgments The authors wish to thank Thomas Sterling for his early contributions to this project. The DIVA project is sponsored by DARPA contract F30602-98-2-0180.  ... 
doi:10.1145/331532.331589 dblp:conf/sc/HallKKDCDLGBSAFSP99 fatcat:6fh4yyrymbd7fkoj4tfmlr5k44

A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System

Jaffrey Draper, J. Tim Barrett, Jeff Sondeen, Sumit Mediratta, Chang Woo Kang, Ihn Kim, Gokhan Daglikoca
2005 Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology  
The Data-Intensive Architecture (DIVA) system employs Processing-In-Memory (PIM) chips as smartmemory coprocessors.  ...  This architecture exploits inherent memory bandwidth both on chip and across the system to target several classes of bandwidth-limited applications, including multimedia applications and pointer-based  ...  Acknowledgments The authors would like to acknowledge the support of the DIVA project team and DARPA (Contract No. F30602-98-2-0180).  ... 
doi:10.1007/s11265-005-4939-1 fatcat:wyjwgtntbvfrngx6ixtikfw5ui

Gilgamesh: A Multithreaded Processor-In-Memory Architecture for Petaflops Computing

T.L. Sterling, H.P. Zima
2002 ACM/IEEE SC 2002 Conference (SC'02)  
Early work on the DIVA project with USC ISI has also contributed to the evolution of the MIND architecture.  ...  The authors would like to thank Maciej Brodowicz, Mike Newell, and Edwin Upchurch for many fruitful discussions on this subject as well as their direct contributions to the modeling of the MIND architecture  ...  In a PIM context, this problem was first addressed in the HTMT and DIVA architectures [7, 17] .  ... 
doi:10.1109/sc.2002.10061 dblp:conf/sc/SterlingZ02 fatcat:p7yhee55zzhplc3cijkiyc6xbq

A new perspective on processing-in-memory architecture design

Dong Ping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph Greathouse, Mitesh Meswani, Mark Nutter, Mike Ignatowski
2013 Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness - MSPC '13  
We explore the potential of using 3D die stacking to move memory-intensive computations closer to memory.  ...  Moving computation closer to main memory presents an opportunity to reduce the overheads associated with data movement.  ...  These problems are exacerbated for emerging workloads that exhibit memory intensive behaviors with irregular access patterns and limited data reuse.  ... 
doi:10.1145/2492408.2492418 dblp:conf/pldi/ZhangJLGMNI13 fatcat:mjqcpy54qbbd3fvodievrmiwxa

Performance Implications of Processing-in-Memory Designs on Data-Intensive Applications

Borui Wang, Martin Torres, Dong Li, Jishen Zhao, Florin Rusu
2016 2016 45th International Conference on Parallel Processing Workshops (ICPPW)  
In this paper, we explore the performance implications of fixed-functional PIM and programmable PIM on three data-intensive benchmarks-including a real data-intensive application.  ...  To introduce PIM into a system, we must answer a fundamental question: what computation logic should be included into PIM?  ...  [6] introduce a PIM-aware data structure that uses low-level PIM APIs to allocate memory and keeps track of data and task mapping. B.  ... 
doi:10.1109/icppw.2016.31 dblp:conf/icppw/WangTLZR16 fatcat:sanauua435dlbiau7trgv6zigu

Moving Processing to Data: On the Influence of Processing in Memory on Data Management [article]

Tobias Vincon, Andreas Koch, Ilia Petrov
2019 arXiv   pre-print
Ideally, it will allow to execute application-defined data- or compute-intensive operations in-situ, i.e. within (or close to) the physical data storage.  ...  Near-Data Processing refers to an architectural hardware and software paradigm, based on the co-location of storage and compute units.  ...  irregular data layouts.  ... 
arXiv:1905.04767v1 fatcat:xksczeu5jjfxhd4bzvaqpuivna

Enabling the Adoption of Processing-in-Memory: Challenges, Mechanisms, Future Research Directions [article]

Saugata Ghose, Kevin Hsieh, Amirali Boroumand, Rachata Ausavarungnirun, Onur Mutlu
2018 arXiv   pre-print
Poor DRAM technology scaling over the course of many years has caused DRAM-based main memory to increasingly become a larger system bottleneck.  ...  We show that both mechanisms improve the performance and energy consumption of many important memory-intensive applications.  ...  This work was also partially supported by the Intel Science and Technology Center for Cloud Computing, the Semiconductor Research Corporation, the Data Storage Systems Center at Carnegie Mellon University  ... 
arXiv:1802.00320v1 fatcat:mdivfek4g5ccfonucnlbjgi3rq

A Survey of Different Approaches for Overcoming the Processor - Memory Bottleneck

Danijela Efnusheva, Ana Cholakoska, Aristotel Tentov
2017 International Journal of Computer Science & Information Technology (IJCSIT)  
This paper provides a brief review of these techniques and also gives a deep analysis of various memorycentric systems that implement different approaches of merging or placing the memory near to the processing  ...  Within this analysis we discuss the advantages, disadvantages and the application (purpose) of several well-known memory-centric systems.  ...  ] • Advantages: flexibility; DIVA PIM chips improve memory bandwidth from 10 up to a 100 times and decrease memory latency, compared to DRAM; DIVA PIM chips are the first smart memory devices that support  ... 
doi:10.5121/ijcsit.2017.9214 fatcat:u6gztzqgyzam3np5fdyzd2sotu


Dongping Zhang, Nuwan Jayasena, Alexander Lyashevsky, Joseph L. Greathouse, Lifan Xu, Michael Ignatowski
2014 Proceedings of the 23rd international symposium on High-performance parallel and distributed computing - HPDC '14  
We explore the use of 3D die stacking to move memory-intensive computations closer to memory.  ...  Moving computation closer to memory presents an opportunity to reduce both energy and data movement overheads.  ...  ACKNOWLEDGEMENTS We would like to thank Yasuko Eckert and Wei Huang for their input on modeling memory stack thermals. We appreciate the invaluable comments from the anonymous reviewers.  ... 
doi:10.1145/2600212.2600213 dblp:conf/hpdc/ZhangJLGXI14 fatcat:gfgw5o2kara6jnft3tcadzhclu

HRL: Efficient and flexible reconfigurable logic for near-data processing

Mingyu Gao, Christos Kozyrakis
2016 2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)  
They should also be flexible to accommodate a wide range of applications.  ...  architectures that move processing closer to main memory.  ...  The authors want to thank Raghu Prabhakar, Christina Delimitrou, and the anonymous reviewers for their insightful comments on earlier versions of this paper.  ... 
doi:10.1109/hpca.2016.7446059 dblp:conf/hpca/GaoK16 fatcat:46yt3s3vznd23ma4aaszp3jfdy

Energy-efficient computing-in-memory architecture for AI processor: device, circuit, architecture perspective

Liang Chang, Chenglong Li, Zhaomin Zhang, Jianbiao Xiao, Qingsong Liu, Zhen Zhu, Weihang Li, Zixuan Zhu, Siqi Yang, Jun Zhou
2021 Science China Information Sciences  
This solution was failed due to the limitation of CMOS technology and application. Recently, the CIM theory is revived thanks to big data and machine learning.  ...  However, data movements between compute part and memory induce memory wall and power wall challenges to the conventional computing architecture.  ...  [34] proposed SUMMARIZER, where the inherent ARM core was located inside an SSD combined as a processor. The data intensive task offloads to the SSD-based processor to accelerate the processing.  ... 
doi:10.1007/s11432-021-3234-0 fatcat:np7wtg24rzavbc5fsmammikn3i

The "MIND" scalable PIM architecture [chapter]

Thomas Sterling, Maciej Brodowicz
2005 Advances in Parallel Computing  
MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction  ...  It is a Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die.  ...  Whittaker of NASA/JPL for lending his unparalleled expertise in the field of logic and VLSI design, and countless hours spent in discussions leading to the refinement of the architectural components of  ... 
doi:10.1016/s0927-5452(05)80010-3 fatcat:m7w6wqjxjrg3zowstdubiknvne

Computer Architecture with Associative Processor Replacing Last-Level Cache and SIMD Accelerator

Leonid Yavits, Amir Morad, Ran Ginosar
2015 IEEE transactions on computers  
Associative Processor combines data storage and processing, and functions as a parallel SIMD processor and a memory at the same time.  ...  This study presents a computer architecture where a last level cache and a SIMD accelerator are replaced by an Associative Processor.  ...  [19] developed DIVA, the Data-Intensive Architecture, combining PIM memories with external host processors.  ... 
doi:10.1109/tc.2013.220 fatcat:fbep2ik5hrcwvowxrzml6mddsm

Architectural support for uniprocessor and multiprocessor active memory systems

Daehyun Kim, M. Chaudhuri, M. Heinrich, E. Speight
2004 IEEE transactions on computers  
(DSMs) Address remapping techniques exploit the data access patterns of applications to enhance their cache performance.  ...  We detail the coherence protocol extensions to support our active memory techniques and present simulation results that show uniprocessor speedup from 1.3 to 7.6 on a range of applications and microbenchmarks  ...  The DIVA [5] , Active Pages [26] , and FlexRAM [13] projects all involve active memory elements-adding processing capability to memory chips, creating so-called PIMs.  ... 
doi:10.1109/tc.2004.1261836 fatcat:2ewquko6ivexff5zifctdxlvie

Near-Memory Address Translation

Javier Picorel, Djordje Jevdjic, Babak Falsafi
2017 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT)  
Processing on a graph involves chasing pointers over a large and irregular data structure [10] .  ...  FlexRAM [104] and DIVA [59] considered an array of microcontrollers next to DRAM, controlled by a host.  ...  Furthermore, we place the page table entries next to the data in the form of an inverted page table, either in SRAM or embedded in DRAM, so that the data fetch and translation operations are completely  ... 
doi:10.1109/pact.2017.56 dblp:conf/IEEEpact/PicorelJF17 fatcat:zgsfj7v4pjazdcfb5hcyemndea
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