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Mapping array communication onto FIFO communication - towards an implementation

J. Kang, A. van der Werf, P. Lippens
Proceedings 13th International Symposium on System Synthesis  
In this paper, we present a method for mapping array communication onto an efficient microcomputer architecture implementation based on FIFO communication via shared memory.  ...  Mapping array communication onto a FIFO-based implementation requires complex address generators if the arrays have multiple dimensions.  ...  The results are shown in Table 2 Conclusion A method for efficiently mapping multi-dimensional array communication onto an implementation using FIFO communication via shared memory has been presented  ... 
doi:10.1109/isss.2000.874051 dblp:conf/isss/KangWL00 fatcat:a7y7z7ujpngydbmok6bd4dftfi

Windowed FIFOs for FPGA-based Multiprocessor Systems

Kai Huang, David Grunert, Lothar Thiele
2007 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP)  
A widely used model for such a deployment is the class of Kahn process networks despite their limitation to pure FIFO communications.  ...  They provide a software abstraction which enables coarse-grained parallel deployment on an FPGA chip.  ...  To build a WFIFO system, a WFIFO process network needs to be mapped onto a target architecture, i.e., for each computation component onto which WFIFO processes are mapped as well as for each communication  ... 
doi:10.1109/asap.2007.4429955 dblp:conf/asap/HuangGT07 fatcat:c6jgf6kq5nboxim7vjs2wrpc3i

A Methodology for Generating Application-Specific Heterogeneous Processor Arrays

S. Craven, C. Patterson, P. Athanas
2006 Proceedings of the 39th Annual Hawaii International Conference on System Sciences (HICSS'06)  
To address these deficiencies, a design methodology is proposed targeting signal processing applications that maps a parallelized C program onto a homogenous array of processors linked by simple point-to-point  ...  To further increase performance for a specific application the chip's array of processors can be tailored to their program, creating an application-specific multiprocessor.  ...  Array after optimization Our method allows for rapid prototyping of the design even before optimizations have begun by simply mapping the C code onto an array of soft processors on an FPGA.  ... 
doi:10.1109/hicss.2006.15 dblp:conf/hicss/CravenPA06 fatcat:osez6ixamvcwtmpv3rvms7bymi

Laura: Leiden Architecture Research and Exploration Tool [chapter]

Claudiu Zissulescu, Todor Stefanov, Bart Kienhuis, Ed Deprettere
2003 Lecture Notes in Computer Science  
In this paper, we present our methodology implemented in the Laura tool, to automatically convert KPNs to synthesizable VHDL code targeted for mapping onto FPGA-based platforms.  ...  At Leiden Embedded Research Center (LERC), we are building a tool chain called Compaan/Laura that allows us to map fast and efficiently applications written in Matlab onto reconfigurable platforms.  ...  Also, we would like to thank to Steven Derrien for his insides toward the processor synchronization issues.  ... 
doi:10.1007/978-3-540-45234-8_88 fatcat:kt4ihlt2y5a3bbakuimxmfyqsi

Wireless Gesture Controlled Systems

Rithesh M Nanda, Harshini H K, Praveen Kuruvadi, Ankhit B V, C Gururaj
2014 IOSR Journal of Electrical and Electronics Engineering  
Gaming systems are going towards complete elimination of controllers and moving towards use of cameras and Ultrasound sensors to detect the movements of gamers, which act as inputs rather than the signals  ...  Present day scenario is tending towards the elimination of Human Interface device to Computers and other devices.  ...  The same here is realized through an array of sensors whose data is processed and mapped to a certain parameter that can be controlled in the physical world.  ... 
doi:10.9790/1676-09643239 fatcat:tudytxsjpbagtou3mpid2jecsu

Creating Customized CGRAs for Scientific Applications

George Charitopoulos, Ioannis Papaefstathiou, Dionisios N. Pnevmatikatos
2021 Electronics  
Executing complex scientific applications on Coarse Grain Reconfigurable Arrays (CGRAs) offers improvements in the execution time and/or energy consumption when compared to optimized software implementations  ...  along, with a separate LUT array being used for adaptability.  ...  • LUT array: an adjacent LUT array able to accommodate all the DFG nodes not directly mapped to the cell logic.  ... 
doi:10.3390/electronics10040445 fatcat:uc33xobotvg45cpf6xsqi4t4hy


E. A. de Kock, W. J. M. Smits, P. van der Wolf, J.-Y. Brunel, W. M. Kruijtzer, P. Lieverse, K. A. Vissers, G. Essink
2000 Proceedings of the 37th conference on Design automation - DAC '00  
We provide an efficient implementation of YAPI in the form of a C++ run-time library to execute the applications on a workstation.  ...  The purpose of YAPI is to enable the reuse of signal processing applications and the mapping of signal processing applications onto heterogeneous systems that contain hardware and software components.  ...  In Section 5 we illustrate the use of YAPI with an example. In Section 6 we discuss the mapping of YAPI onto target architectures.  ... 
doi:10.1145/337292.337511 dblp:conf/dac/KockSWBKLVE00 fatcat:tmf6b7vvsfealf5ys7gtoi5ifm

Low Overhead Message Passing for High Performance Many-Core Processors

Sumeet S. Kumar, Mitzi Tjin A. Djie, Rene Van Leuken
2013 2013 First International Symposium on Computing and Networking  
The overheads for communication in a 16-core processor array are under 5% for 64-word burst transfers with Pronto using workloads such as the JPEG decoder and FIR filter.  ...  Furthermore, this paper also studies the effect of task mapping and interconnect traffic on the predictability of data block arrival times, and illustrates a method to reduce variations.  ...  During compilation, tasks are mapped onto cores and their communication flows converted into interconnect schedules.  ... 
doi:10.1109/candar.2013.62 dblp:conf/ic-nc/KumarDL13 fatcat:usxvubgwazaizgdh4gvqj32vc4

Towards Efficient Design Space Exploration of Heterogeneous Embedded Media Systems [chapter]

A. D. Pimentel, S. Polstra, F. Terpstra, A. W. van Halderen, J. E. Coffland, L. O. Hertzberger
2002 Lecture Notes in Computer Science  
Moreover, using a case study in which we have applied an initial version of our prototype modeling and simulation environment to an M-JPEG encoding application, we illustrate the ease with which alternative  ...  In this paper, we present an overview of the modeling and simulation methodology used in Artemis.  ...  The second one gives the number of FIFO buffers connected to a virt proc object, after which these FIFO buffers are specified in an array.  ... 
doi:10.1007/3-540-45874-3_4 fatcat:jszqiy34ufhrtecjsq325j2tty

Towards compilation of streaming programs into FPGA hardware

Franjo Plavec, Zvonko Vranesic, Stephen Brown
2008 2008 Forum on Specification, Verification and Design Languages  
There is an increasing need for automated conversion of high-level design descriptions into hardware.  ...  Another approach is to take an existing parallel programming model and map a program written in it onto hardware [14] .  ...  We use FIFO buffers because of their small size, which allows us to implement them in an on-chip memory in the FPGA.  ... 
doi:10.1109/fdl.2008.4641423 dblp:conf/fdl/PlavecVB08 fatcat:nqlttknnprbndc2eih62jfl7ea

FPGA-Based Soft-Core Processors for Image Processing Applications

Moslem Amiri, Fahad Manzoor Siddiqui, Colm Kelly, Roger Woods, Karen Rafferty, Burak Bardak
2016 Journal of Signal Processing Systems  
Whilst a Field-Programmable Gate Array has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and  ...  An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification  ...  Implementation This design maps data flow control and three functional units onto an ARM core.  ... 
doi:10.1007/s11265-016-1185-7 pmid:32226579 pmcid:PMC7089673 fatcat:5oenzxqh4natzdxpai2u6gyntu

A Hierarchical Architectural Framework for Reconfigurable Logic Computing

Peng Li, Angshuman Parashar, Michael Pellauer, Tao Wang, Joel Emer
2013 2013 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum  
and to clearly separate architectural choices from implementation ones.  ...  While there is a rich body of prior work proposing a variety of reconfigurable systems, we believe there hasn't been an attempt to clearly identify the architectural tradeoff spaces for an RL compute engine  ...  Each option naturally has implementation ramifications, as well as performance implications for workloads mapped onto the architecture.  ... 
doi:10.1109/ipdpsw.2013.252 dblp:conf/ipps/LiPPWE13 fatcat:iznf6jppmzffba6bd6g5mn32sa

Rigorous system level modeling and analysis of mixed HW/SW systems

P. Bourgos, A. Basu, M. Bozga, S. Bensalem, J. Sifakis, K. Huang
2011 Ninth ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMPCODE2011)  
A grand challenge in complex embedded systems design is developing methods and tools for modeling and analyzing the behavior of an application software running on multicore or distributed platforms.  ...  Its implementation must deal with mapping the specified application-level parallelism onto platformlevel (threads, cores, processors) on an as-needed/asavailable basis.  ...  Moreover, for every memory component, we consider the union of all the FIFO buffers mapped onto it according to the mapping.  ... 
doi:10.1109/memcod.2011.5970506 dblp:conf/memocode/BourgosBBBSH11 fatcat:ehj6b4qbf5hsnals6d3ciilaya

Towards scalable utilization of embedded manycores in throughput-sensitive applications

Matin Hashemi, Soheil Ghiasi
2011 2011 IEEE International High Level Design Validation and Test Workshop  
For tasks that are assigned to the same processor, inter-task communication is implemented using arrays.  ...  That is, the producer task writes its data to an array, which is then read by the consumer task. Inter-processor communication is implemented using read and write system calls.  ... 
doi:10.1109/hldvt.2011.6113985 dblp:conf/hldvt/HashemiG11 fatcat:oh6mk7askrg5jfeabfxjqbpyt4

A case for spiking neural network simulation based on configurable multiple-FPGA systems

Shufan Yang, Qiang Wu, Renfa Li
2011 Cognitive Neurodynamics  
An alternative approach, hardware implementation of such system, provides the possibility to generate independent spikes precisely and simultaneously output spike waves in real time, under the premise  ...  A current implementation of communication controller contains eight 32bit FIFOs. This can be configured during simulation to an appropriate size, depending on the logical resources of FPGA devices.  ...  Translating this aspect to the case of communication controller, the communication controller may have a larger FIFO on the receiver side and transmitter side.  ... 
doi:10.1007/s11571-011-9170-0 pmid:22942919 pmcid:PMC3179547 fatcat:czem7mnllbdltpsmpkx3i67rga
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