Filters








2,844 Hits in 9.1 sec

Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Anup Holey, Vineeth Mekkat, Pen-Chung Yew, Antonia Zhai
2015 ACM Transactions on Architecture and Code Optimization (TACO)  
The shared last-level cache (LLC) is one of the most important shared resources due to its impact on performance.  ...  In this work, we propose heterogeneous LLC management (HeLM), a novel shared LLC management policy that takes advantage of the GPU's tolerance for memory access latency.  ...  In heterogeneous multicore systems, the efficient sharing of on-chip resources, such as the last-level cache (LLC), is key to performance.  ... 
doi:10.1145/2710019 fatcat:m3f434lbcvhpfcib7v3uhq4nle

On Improving Efficiency and Utilization of Last Level Cache in Multicore Systems

Yumna Zahid, Hina Khurshid, Zulfiqar Ali Memon
2018 Information Technology and Control  
The current on-chip architecture comprises multiple cores which usually share last level cache which can be physically distributed on chip.  ...  Maintaining energy efficient system is a crucial challenge for multicore processors.  ...  The shared Last level cache, which provides megabytes to multicore, is hard to manage since it requires cache coherency protocols on architectural level.  ... 
doi:10.5755/j01.itc.47.3.18433 fatcat:pgrmyliv3ra5vjlkqqv3vhuudu

Multicores in Cloud Computing: Research Challenges for Applications

Lizhe Wang, Jie Tao, Gregor Von Laszewski, Holger Marten
2010 Journal of Computers  
At the same time, the dominating resource sharing platforms, in the form of compute Grids, are facing a grand challenge from Cloud computing.  ...  A cluster of multicores will be commonly used as an efficient computational platform for high performance computing in the near future.  ...  Figure 1 shows both architectures with a four core processor as example. As shown in the figure, a multicore architecture contains several CPU cores each equipped with a private first level cache.  ... 
doi:10.4304/jcp.5.6.958-964 fatcat:w7uw2hf7analhadyn7nqrabvym

Scalable and Flexible heterogeneous multi-core system

Rashmi, Dr. Dinesh
2012 International Journal of Advanced Computer Science and Applications  
Use of high memory-level parallelism (MLP) reduces the memory wall. Micro architecture contains a set of small and fast cache processors which execute high locality code.  ...  A network of small in-order memory engines use low locality code to improve performance by using instruction level parallelism (ILP).  ...  On multi-core processors, the last-level cache, which is the level before requiring off-chip main memory access, is usually shared among more cores.  ... 
doi:10.14569/ijacsa.2012.031227 fatcat:m4vqub3x2fc7jlwm7dsb47ngzy

Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems

Sangyeun Cho, Tao Li, Onur Mutlu
2008 IEEE Micro  
The authors studied a series of scheduling policies that exploit OS observations, with the purpose of mitigating performance variability caused by the shared last-level cache and the processors' functional  ...  These articles span topics including hardware-software cooperative management of shared on-chip resources, implications of dynamically heterogeneous multicore processors for thread scheduling, the use  ... 
doi:10.1109/mm.2008.39 fatcat:v74yt5jbxbe55addifn6onsyka

A survey on hardware-aware and heterogeneous computing on multicore processors and accelerators

Rainer Buchty, Vincent Heuveline, Wolfgang Karl, Jan-Philipp Weiss
2011 Concurrency and Computation  
In this work we provide a survey on current multicore and accelerator technologies.  ...  This problem is impaired by increasing heterogeneity of hardware platforms on both, processor level, and by adding dedicated accelerators.  ...  Acknowledgements The Shared Research Group 16-1 received financial support by the Concept for the Future of Karlsruhe Institute of Technology in the framework of the German Excellence Initiative and the  ... 
doi:10.1002/cpe.1904 fatcat:fwg2vjaobral3b2v46vq4x2c3q

Resource-Aware Replication on Heterogeneous Multicores: Challenges and Opportunities [article]

Björn Döbel, Robert Muschner, Hermann Härtig
2014 arXiv   pre-print
Decreasing hardware feature sizes and increasing heterogeneity in multicore hardware require software that can adapt to these platforms' properties.  ...  In this paper we review challenges and opportunities for ROMAIN to adapt to such multicore platforms in order to decrease execution overhead, resource requirements, and vulnerability against faults.  ...  We found these benchmarks to cause a huge amount of last-level cache misses.  ... 
arXiv:1405.2913v1 fatcat:ha7rsuy6rjaxroppvkwi6alzqu

Trends in multicore DSP platforms

Lina Karam, Ismail Alkamal, Alan Gatherer, Gene Frantz, David Anderson, Brian Evans
2009 IEEE Signal Processing Magazine  
In 1997, he won the U.S. NSF CAREER Award. He is a Fellow of the IEEE.  ...  32 kB L1 D-Cache 512 kB L2 Cache/ M2 Memory [FIG7] picoChip PC205 multicore DSP processor.  ...  In contrast, in a hierarchical interconnected architecture, in which the cores mostly communicate by means of a shared L2/L3 memory and have to cache data from the shared memory, the tasks can be assigned  ... 
doi:10.1109/msp.2009.934113 fatcat:2hsjudqn7nfclbjhm5lkivi2ee

Power and energy containers for multicore servers

Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, Xiao Zhang
2012 Proceedings of the 12th ACM SIGMETRICS/PERFORMANCE joint international conference on Measurement and Modeling of Computer Systems - SIGMETRICS '12  
We evaluate our request-level power/energy containers on three different multicore processors (Intel Woodcrest, Nehalem, and Westmere) using a number of opensource application workloads including a high  ...  New computing platforms with multicore resource sharing and heterogeneity further obfuscate the system behaviors, presenting challenges for request/client-based energy accounting, identification and control  ...  The first is a multichip/multicore machine with two dual-core (four cores total) Intel Xeon 5160 3.0 GHz "Woodcrest" processors. Two cores on each processor chip share a single 4 MB L2 cache.  ... 
doi:10.1145/2254756.2254814 dblp:conf/sigmetrics/ShenSDZ12 fatcat:phw5kslcr5g23hia4z5tfieeey

Power and energy containers for multicore servers

Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, Xiao Zhang
2012 Performance Evaluation Review  
We evaluate our request-level power/energy containers on three different multicore processors (Intel Woodcrest, Nehalem, and Westmere) using a number of opensource application workloads including a high  ...  New computing platforms with multicore resource sharing and heterogeneity further obfuscate the system behaviors, presenting challenges for request/client-based energy accounting, identification and control  ...  The first is a multichip/multicore machine with two dual-core (four cores total) Intel Xeon 5160 3.0 GHz "Woodcrest" processors. Two cores on each processor chip share a single 4 MB L2 cache.  ... 
doi:10.1145/2318857.2254814 fatcat:k674dnfhkngl7jy6m65buakkzy

Power containers

Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, Xiao Zhang, Zhuan Chen
2013 SIGPLAN notices  
Our evaluation uses three multicore processors (Intel Woodcrest, Westmere, and SandyBridge) and a variety of server and cloud computing (Google App Engine) workloads.  ...  Our mechanisms enable new multicore server management capabilities including fair power capping that only penalizes powerhungry requests, and energy-aware request distribution between heterogeneous servers  ...  Acknowledgments This work was supported in part by the U.S. National Science Foundation grants CNS-0834451, CCF-1016902, CNS-1217372, CCF-1217920, CNS-1239423.  ... 
doi:10.1145/2499368.2451124 fatcat:7di7tar3ujciha7twak4fdtgd4

Power containers

Kai Shen, Arrvindh Shriraman, Sandhya Dwarkadas, Xiao Zhang, Zhuan Chen
2013 Proceedings of the eighteenth international conference on Architectural support for programming languages and operating systems - ASPLOS '13  
Our evaluation uses three multicore processors (Intel Woodcrest, Westmere, and SandyBridge) and a variety of server and cloud computing (Google App Engine) workloads.  ...  Our mechanisms enable new multicore server management capabilities including fair power capping that only penalizes powerhungry requests, and energy-aware request distribution between heterogeneous servers  ...  Acknowledgments This work was supported in part by the U.S. National Science Foundation grants CNS-0834451, CCF-1016902, CNS-1217372, CCF-1217920, CNS-1239423.  ... 
doi:10.1145/2451116.2451124 dblp:conf/asplos/ShenSDZC13 fatcat:szcuwz2hbbbclpbfsfummeyauy

MAESTRO: Orchestrating predictive resource management in future multicore systems

Sangyeun Cho, Socrates Demetriades
2011 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)  
In this position paper, we make a case for a novel framework called MAESTRO which predictively manages system resources in shared-memory parallel computing platforms built with advanced multicore processors  ...  the learning to relevant program and system control structures, and makes resource management decisions such as task mapping and cache partitioning in a predictive manner.  ...  Last-level cache memory is an important shared resource in a multicore system.  ... 
doi:10.1109/ahs.2011.5963917 dblp:conf/ahs/ChoD11 fatcat:7qfcxjpkdjd33lwzubornspiom

Two novel cache management mechanisms on CPU-GPU heterogeneous processors

Huijing Yang, Tingwen Yu
2021 Research Briefs on Information & Communication Technology Evolution  
Heterogeneous multicore processors that take full advantage of CPUs and GPUs within the same chip raise an emerging challenge for sharing a series of on-chip resources, particularly Last-Level Cache (LLC  ...  Under the current cache management policies, the LLC sharing of CPU applications can be remarkably decreased due to the existence of GPU workloads, thus seriously affecting the overall performance.  ...  We would also like to thank all teachers and students in our laboratory for helpful discussions.  ... 
doi:10.22667/rebicte.2021.06.15.001 doaj:894b43889d8f4f608eff843bea80cdc3 fatcat:6xc6imq3kjgsfak66tq5wvykhy

Load balancing strategy for multicore systems

E. Chovancova, J. Mihal'ov
2015 2015 13th International Conference on Emerging eLearning Technologies and Applications (ICETA)  
In this paper we have summarized a number of load balancing algorithms that minimize the power consumption of multicore technology while maintaining performance to the best level.  ...  The birth of multicore systems is a major cause of huge power consumption and producing a lot of heat. Cores are the fundamental units that read and execute instructions in a computer program.  ...  ACKNOWLEDGMENT The work is supported by iFuture: A Leading Research Group in Department of Computer Science, Abdul Wali Khan University, Mardan. The authors are thankful to Miss.  ... 
doi:10.1109/iceta.2015.7558473 fatcat:ffoxzd7j6jc4loehhunoppfhwe
« Previous Showing results 1 — 15 out of 2,844 results