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Main memory adaptive indexing for multi-core systems

Victor Alvarez, Felix Martin Schuhknecht, Jens Dittrich, Stefan Richter
2014 Proceedings of the Tenth International Workshop on Data Management on New Hardware - DaMoN '14  
Until now, however, most adaptive indexing algorithms have been designed single-threaded, yet with multi-core systems already well established, the idea of designing parallel algorithms for adaptive indexing  ...  In this paper we describe three alternative parallel algorithms for adaptive indexing, including a second variant of a parallel standard cracking algorithm.  ...  Acknowledgement We would like to thank Felix Halim and Stratos Idreos for kindly providing the source code for P-SC used in [5, 6] . Research partially supported by BMBF.  ... 
doi:10.1145/2619228.2619231 dblp:conf/damon/AlvarezSD014 fatcat:htxfn3tlobh53owj3tehornlqa

Main Memory Adaptive Indexing for Multi-core Systems [article]

Victor Alvarez, Felix Martin Schuhknecht, Jens Dittrich, Stefan Richter
2014 arXiv   pre-print
Until now, however, most adaptive indexing algorithms have been designed single-threaded, yet with multi-core systems already well established, the idea of designing parallel algorithms for adaptive indexing  ...  Parallel sorting algorithms serve as a realistic baseline for multi-threaded adaptive indexing techniques. In total we experimentally compare seven parallel algorithms.  ...  Acknowledgement We would like to thank Felix Halim and Stratos Idreos for kindly providing the source code for P-SC used in [6, 7] .  ... 
arXiv:1404.2034v1 fatcat:rtjkv3xnzfhnjjuarpdq43dhui

ILX: Intelligent "Location+X" Data Systems (Vision Paper) [article]

Walid G. Aref, Ahmed M. Aly, Anas Daghistani, Yeasir Rayhan, Jianguo Wang, Libin Zhou
2022 arXiv   pre-print
The ubiquity of location data and location data services call for systems that are solely designed and optimized for the efficient support of location data.  ...  Typically, relational or NoSQL data systems that are mostly designed with non-location data in mind get extended with spatial or spatiotemporal indexes, some query operators, and higher level syntactic  ...  Thus, efficient location data layout in main-memory and cache-aware location-based indexes are important factors for a highly performant ILX system. 3.2.4 Persistent Memory.  ... 
arXiv:2206.09520v2 fatcat:6f7aqxy225hbbci4zxf2dtz4ie

Main Memory Database Systems

Frans Faerber, Alfons Kemper, Per-Åke Larson, Justin Levandoski, Tjomas Neumann, Andrew Pavlo
2017 Foundations and Trends in Databases  
Several systems also implement novel indexing methods that optimize for CPU cache efficiency [85] as well as multi-core parallelism using latch-free designs [89] . • Concurrency control.  ...  Massively Parallel Sort-Merge Joins in Main Memory Multi-Core Database Systems. Joy Arulraj, Andrew Pavlo, and Subramanya Dulloor.  ... 
doi:10.1561/1900000058 fatcat:j7dpcbszkbdqdarwrxdt3dv5ja

Multi-device Controllers: A Library to Simplify Parallel Heterogeneous Programming

Ana Moreton-Fernandez, Arturo Gonzalez-Escribano, Diego R. Llanos
2017 International journal of parallel programming  
NVIDIA's GPUs, or OpenMP for CPU-cores).  ...  Programming efficiently for these heterogeneous systems has become an important challenge.  ...  Acknowledgments This research has been partially supported by MICINN (Spain) and ERDF program of the European Union: HomProg-HetSys project (TIN2014-58876-P) and COST Program Action IC1305: Network for  ... 
doi:10.1007/s10766-017-0542-x fatcat:r4tlgwkz5jhojhfp4s5xdx666y

Adaptive Block Pinning Based: Dynamic Cache Partitioning for Multi-core Architectures

Nitin Chaturvedi, Jithin Thomas, S Gurunarayanan
2010 International Journal of Computer Science & Information Technology (IJCSIT)  
a novel partitioning scheme known as Adaptive Block Pinning which would result in a better utilization of the cache resources in CMPs.  ...  The widening speed gap between processors and memory along with the issue of limited on-chip memory bandwidth make the last-level cache utilization a crucial factor in designing future multicore processors  ...  This increment in the available processing power proves quite attractive for multi-application workloads, which in turn exerts additional pressure on the memory, especially the on-chip memory system.  ... 
doi:10.5121/ijcsit.2010.2604 fatcat:tbgzbr2xvjcjhegy52ffylargq

Databases and hardware

Anastasia Ailamaki
2015 Proceedings of the VLDB Endowment  
Fast query and transaction processing is the goal of 40 years of database research and the reason of existence for many new database system architectures.  ...  In 1980, the goal was to minimize disk accesses; in 2000, memory replaced disks in terms of access costs.  ...  We discuss how well modern diskand main-memory-oriented transaction processing systems utilize the cache hierarchies and the abundant non-uniform parallelism of modern multi-socket multi-core servers.  ... 
doi:10.14778/2824032.2824142 fatcat:ugl7ujexjng57fqbebzt3oecre

Challenges for a GPU-Accelerated Dynamic Programming Approach for Join-Order Optimization

Andreas Meister, Gunter Saake
2016 Workshop Grundlagen von Datenbanken  
Unfortunately, adapting existing dynamic programming approaches for join-order optimization to GPUs is not straightforward.  ...  The state of the art in commercial systems for determining optimal join orders is dynamic programming.  ...  Using the parallel execution of multi-core CPUs and their adapted approach, Han et al. achieve an almost linear speed up for the dynamic programming approach on multi-core CPUs.  ... 
dblp:conf/gvd/0001S16 fatcat:a6ewabqyjfddtjbdoy2qdzdrom

ERIS live

Tim Kiefer, Thomas Kissinger, Benjamin Schlegel, Dirk Habich, Daniel Molka, Wolfgang Lehner
2014 Proceedings of the 2014 ACM SIGMOD international conference on Management of data - SIGMOD '14  
All experiments are conducted on a standard server system as well as on a system consisting of 64 multiprocessors, 512 cores, and 8 TBs main memory.  ...  In-memory database systems running on NUMA platforms face several issues such as the increased latency and the decreased bandwidth when accessing remote main memory.  ...  ACKNOWLEDGMENTS This work is partly funded by the German Research Foundation (DFG) in the Collaborative Research Center 912 "Highly Adaptive Energy-Efficient Computing" and under project number LE 1416  ... 
doi:10.1145/2588555.2594524 dblp:conf/sigmod/KieferKSHML14 fatcat:imoamwng3jbz5oppq7mrrutjlu

EMVS: Embedded Multi Vector-core System

Tassadaq Hussain, Amna Haider, Adrian Cristal, Eduard Ayguadé
2018 Journal of systems architecture  
In this work, we proposed an embedded multi vector-core system (EMVS) which executes the embedded application by managing the multiple vectorized tasks and their memory operations.  ...  With the increase in the density and performance of digital electronics, the demand for a power-efficient high-performance computing (HPC) system has been increased for embedded applications.  ...  Section 7 summarizes our main conclusions. Embedded Multi Vector-core Processor System The Embedded Multi Vector-core Processor System (EMVS) is shown in Figure 1 .  ... 
doi:10.1016/j.sysarc.2018.04.002 fatcat:44lbldctjnekjpfwrnmicmkhc4

Using GPU for Multi-Agent Soil Simulation

G. Laville, K. Mazouzi, C. Lang, L. Philipppe, N. Marilleau
2013 2013 21st Euromicro International Conference on Parallel, Distributed, and Network-Based Processing  
In this paper we present the use of GPU for the execution of Sworm, a multi-scale MAS system.  ...  We advocate for a wider use of the GPU in Agent Based Models in particular for multi-scale systems with work distribution between the CPU and GPU.  ...  ACKNOWLEDGMENT The authors would like to thanks the Mésocentre de calcul de Franche-Comté, which provided the computer facilities used for the computations described in the paper.  ... 
doi:10.1109/pdp.2013.63 dblp:conf/pdp/LavilleMLPM13 fatcat:ivzqhmmgfjb2pod36nrfemiq2e

GPGPU for Difficult Black-box Problems

Marcin Pietroń, Aleksander Byrski, Marek Kisiel-Dorohinicki
2015 Procedia Computer Science  
The presented research is a part of building heterogenous parallel algorithm for difficult black-box Golomb Ruler problem.  ...  In this paper, efficient use of a hardware accelerator to implement dedicated solvers for such problems is discussed and studied based on an example of Golomb Ruler problem.  ...  The single cores in multi-core systems may implement architectures such as vector processing, SIMD, or multi-threading.  ... 
doi:10.1016/j.procs.2015.05.249 fatcat:rd6xn7xpinbcxpj75usayumm3i

Design and management of 3D-stacked NUCA cache for chip multiprocessors

Jongpil Jung, Kyungsu Kang, Chong-Min Kyung
2011 Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '11  
Experimental results show that the proposed method enhances system performance by 23.3% and reduces energy consumption by 17.9% for 16-core processor system compared to conventional design.  ...  In addition, this paper investigates the problem of partitioning shared L2 cache for concurrently executing multiple applications in order to improve the system performance in terms of instructions per  ...  Conventional cache reconfiguration researches adapted waylevel cache division for multi-processor systems with uniform cache architecture.  ... 
doi:10.1145/1973009.1973028 dblp:conf/glvlsi/JungKK11 fatcat:f6hjnfyiavb67mzn3tn7vaeiga

Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead

Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
2016 ACM Transactions on Architecture and Code Optimization (TACO)  
Research proposals, implement coherence protocols for sequential consistency (SC) between CPU cores, and between devices.  ...  This work proposes a novel scheme to facilitate heterogeneous systems with unified virtual memory.  ...  GPU SMs generate traffic to it). memory, and between main memory and device memory (in non-fused contemporary systems).  ... 
doi:10.1145/2889488 fatcat:cx5535ifhfgnxe3yocrc6h77sq

The New Hardware Development Trend and the Challenges in Data Management and Analysis

Wei Pan, Zhanhuai Li, Yansong Zhang, Chuliang Weng
2018 Data Science and Engineering  
Then, the related research techniques which affect the upper data management system design are reviewed.  ...  Finally, challenges and opportunities are addressed for the key technologies of data management and analysis in new hardware environments.  ...  Acknowledgements The authors would like to thank Mike Dixon for  ... 
doi:10.1007/s41019-018-0072-6 fatcat:kksuldstdvdohpkleq7suyq2ry
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