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Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time

Hyemin Choe, Jeongju Jee, Seung-Chan Lim, Sung Min Joe, Il Han Park, Hyuncheol Park
2020 IEEE Access  
MACHINE-LEARNING-BASED READ REFERENCE VOLTAGE ESTIMATION FRAMEWORK In this section, we propose the machine-learning-based read reference voltage estimation framework for NAND flash memory systems without  ...  To overcome the aforementioned drawbacks of conventional schemes, we propose a novel machine-learning-based read reference voltage estimation framework for NAND flash memory without the knowledge of retention  ... 
doi:10.1109/access.2020.3026232 fatcat:sldcc5qtqnhh3fgpdpoljti3za

Architectural Techniques for Improving NAND Flash Memory Reliability [article]

Yixin Luo
2018 arXiv   pre-print
Raw bit errors are common in NAND flash memory and will increase in the future. These errors reduce flash reliability and limit the lifetime of a flash memory device.  ...  We investigate four directions through this approach. (1) We propose a new technique called WARM that improves flash reliability by 12.9 times by managing flash retention differently for write-hot data  ...  Our models can accurately predict/estimate the optimal read reference voltage and the raw bit error rate based on the retention time and the layer number of each flash memory page.  ... 
arXiv:1808.04016v1 fatcat:fotned4yajc2xmaoezwjdrgypu

Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery [article]

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
2018 arXiv   pre-print
Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory.  ...  We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques.  ...  ACKNOWLEDGMENTS The authors would like to thank Rino Micheloni for his helpful feedback on earlier drafts of the paper. They would also like to thank Seagate for their continued dedicated support.  ... 
arXiv:1711.11427v2 fatcat:rvnbeg4eevfa7lczf2h2ificxi

Error Characterization, Mitigation, and Recovery in Flash Memory Based Solid-State Drives [article]

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
2017 arXiv   pre-print
Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory.  ...  We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques.  ...  ACKNOWLEDGMENTS The authors would like to thank Rino Micheloni for his helpful feedback on earlier drafts of the paper.  ... 
arXiv:1706.08642v3 fatcat:ozzc62npvzewhgkb54ebvnh5ta

Read Disturb Errors in MLC NAND Flash Memory [article]

Yu Cai, Yixin Luo, Saugata Ghose, Erich F. Haratsch, Ken Mai, Onur Mutlu
2018 arXiv   pre-print
For the first time in open literature, this work experimentally characterizes read disturb errors on state-of-the-art 2Y-nm (i.e., 20-24 nm) MLC NAND flash memory chips.  ...  NAND flash memory reliability continues to degrade as the memory is scaled down and more bits are programmed per cell.  ...  Acknowledgments We thank the anonymous reviewers for their feedback.  ... 
arXiv:1805.03283v1 fatcat:swhmawggyrbdfi25gx6jtditg4

Chip-off Success Rate Analysis Comparing Temperature and Chip Type

Choli Ence, Gary Cantrell
2018 Journal of Digital Forensics, Security and Law  
Thermal based chipanalysis relies upon the application of heat to remove the flash memory chip from the circuit board.  ...  Occasionally, a flash memory chip fails to successfully read despite following similar protocols as other flash memory chips.  ...  VLSI implementation of BCH error correction for multilevel cell NAND flash memory. IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, 18(5) , 843-847.  ... 
doi:10.15394/jdfsl.2018.1545 fatcat:bku6o3ujavagnax7o35h4rqoga

Advances in Emerging Memory Technologies: From Data Storage to Artificial Intelligence

Gabriel Molas, Etienne Nowak
2021 Applied Sciences  
It begins with the presentation of stand-alone and embedded memory technology evolution, since the appearance of Flash memory in the 1980s.  ...  Then, the progress of emerging memory technologies (based on filamentary, phase change, magnetic, and ferroelectric mechanisms) is presented with a review of the major demonstrations in the literature.  ...  Memory mapped SCM should combine read/write and endurance performances close to DRAM, with improved retention time (without being a true nonvolatile memory) and lower cost.  ... 
doi:10.3390/app112311254 fatcat:pg4iqzg4yfc2vb2lh2mgkyqafq

Neighbor-cell assisted error correction for MLC NAND flash memories

Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman Unsal, Adrian Cristal, Ken Mai
2014 The 2014 ACM international conference on Measurement and modeling of computer systems - SIGMETRICS '14  
To distinguish between different potential stored values, conventional techniques to read data from flash memory employ a single set of reference voltage values, which are determined based on the overall  ...  distributions can be used to determine a set of read reference voltages that lead to error rates much lower than when a single set of reference voltage values based on the overall distribution are used  ...  This work was partially supported by the Intel Science and Technology Center for Cloud Computing, Data Storage Systems Center (DSSC) at Carnegie Mellon University, NSF Award CCF 12122962, the FP7 ParaDIME  ... 
doi:10.1145/2591971.2591994 dblp:conf/sigmetrics/CaiYMHUCM14 fatcat:ol5i3wjmozefjmdiy6rkjhiizq

Neighbor-cell assisted error correction for MLC NAND flash memories

Yu Cai, Gulay Yalcin, Onur Mutlu, Erich F. Haratsch, Osman Unsal, Adrian Cristal, Ken Mai
2014 Performance Evaluation Review  
To distinguish between different potential stored values, conventional techniques to read data from flash memory employ a single set of reference voltage values, which are determined based on the overall  ...  distributions can be used to determine a set of read reference voltages that lead to error rates much lower than when a single set of reference voltage values based on the overall distribution are used  ...  This work was partially supported by the Intel Science and Technology Center for Cloud Computing, Data Storage Systems Center (DSSC) at Carnegie Mellon University, NSF Award CCF 12122962, the FP7 ParaDIME  ... 
doi:10.1145/2637364.2591994 fatcat:y6okwyliyfa4td2zvgknyb565e

Research Problems and Opportunities in Memory Systems

2014 Supercomputing Frontiers and Innovations  
We also briefly describe our ongoing related work in combating scaling challenges of NAND flash memory.  ...  system (an approach we call system-DRAM co-design), 2) designing a memory system that employs emerging non-volatile memory technologies and takes advantage of multiple different technologies (i.e., hybrid  ...  We would like to thank Rachata Ausavarungnirun for logistic help in preparing this article and earlier versions of it.  ... 
doi:10.14529/jsfi140302 fatcat:2zfa7zk3qjgohdsgxmkkqaamuu

Mitigating Self-Heating in Solid State Drives for Industrial Internet-of-Things Edge Gateways

Cristian Zambelli, Lorenzo Zuolo, Luca Crippa, Rino Micheloni, Piero Olivo
2020 Electronics  
Concerns on storage temperature are to be considered especially when Solid State Drives (SSD)based on 3D NAND Flash technology are part of edge gateway architectures.  ...  that can be applied in synergy with the operating system of the host.  ...  The 3D NAND Flash memory sub-system whose power contribution depends on the amount of parallel accessed channels and on the operation performed (i.e., data read, write/program or erase); 3.  ... 
doi:10.3390/electronics9071179 fatcat:562qhdhmyzdezjisvzckmj5q6a

Evaluating technological emergence using text analytics: two case technologies and three approaches

Samira Ranaei, Arho Suominen, Alan Porter, Stephen Carley
2019 Scientometrics  
The term count based method identifies detailed emergence patterns.  ...  This study evaluates the use of three different reproducible approaches for identifying the emergence of technological novelties in scientific publications.  ...  Appendix: Results of term count based methods See Tables 5, 6, 7 and 8  ... 
doi:10.1007/s11192-019-03275-w fatcat:6yvsj5csx5dsdhdasn3ftbih2u

A Survey of Test and Reliability Solutions for Magnetic Random Access Memories

Patrick Girard, Yuanqing Cheng, Arnaud Virazel, Weisheng Zhao, Rajendra Bishnoi, Mehdi B. Tahoori
2020 Proceedings of the IEEE  
| Memories occupy most of the silicon area in nowadays' system-on-chips and contribute to a significant part of system power consumption.  ...  Though widely used, nonvolatile Flash memories still suffer from several drawbacks. Magnetic random access memories (MRAMs) have the potential to mitigate most of the Flash shortcomings.  ...  A faulty read operation happens when the voltage generated for reading an antiparallel state ("1") becomes lower than the reference voltage or when the voltage generated for reading a parallel state ("  ... 
doi:10.1109/jproc.2020.3029600 fatcat:vylorloh3bfqda7ossdczxspm4

A Modern Primer on Processing in Memory [article]

Onur Mutlu, Saugata Ghose, Juan Gómez-Luna, Rachata Ausavarungnirun
2020 arXiv   pre-print
The emergence of 3D-stacked memory plus logic, the adoption of error correcting codes inside the latest DRAM chips, proliferation of different main memory standards and chips, specialized for different  ...  At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance.  ...  based on the current wearout of each NAND flash cell, optimizing voltage levels to maximize memory lifetime, employing sophisticated error correction and recovery techniques to maximize lifetime and minimize  ... 
arXiv:2012.03112v1 fatcat:hq2i2xzq4nbszenq7rqmjzcjci

Underdesigned and Opportunistic Computing in Presence of Hardware Variability

Puneet Gupta, Yuvraj Agarwal, Lara Dolecek, Nikil Dutt, Rajesh K. Gupta, Rakesh Kumar, Subhasish Mitra, Alexandru Nicolau, Tajana Simunic Rosing, Mani B. Srivastava, Steven Swanson, Dennis Sylvester
2013 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
This paper explores the possibility of constructing computing machines that purposely expose hardware variations to various layers of the system stack including software.  ...  Microelectronic circuits exhibit increasing variations in performance, power consumption, and reliability parameters across the manufactured parts and across use of these parts over time in the field.  ...  scheduler selects the actual duty cycle based on run-time monitoring of operational parameters, and a power-temperature model that is learned off-line for the specific processor instance.  ... 
doi:10.1109/tcad.2012.2223467 fatcat:gtncdvvjvvgjth6ihii7y24g54
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