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iMAD: An In-Memory Accelerator for AdderNet with Efficient 8-bit Addition and Subtraction Operations

Shien Zhu, Shiqing Li, Weichen Liu
2022 Proceedings of the Great Lakes Symposium on VLSI 2022  
In this paper, we propose iMAD as an in-memory accelerator for AdderNet with efficient addition and subtraction operations.  ...  Second, we propose an accelerator architecture for AdderNet with high parallelism based on the optimized operators.  ...  Conclusion We present iMAD as an STT-MRAM based in-memory accelerator for AdderNet.  ... 
doi:10.1145/3526241.3530313 fatcat:td3foc4mmfhhrcgtwf3wz7j67q

FAT: An In-Memory Accelerator with Fast Addition for Ternary Weight Neural Networks [article]

Shien Zhu, Luan H.K. Duong, Hui Chen, Di Liu, Weichen Liu
2022 arXiv   pre-print
They replace the multiplication operations in CNNs with additions, which are favoured on In-Memory-Computing (IMC) devices. IMC acceleration for BWNs has been widely studied.  ...  Second, we propose a fast addition scheme based on the memory Sense Amplifier to avoid the time overhead of both carry propagation and writing back the carry to the memory cells.  ...  Overview Our accelerator, FAT, is an STT-MRAM based In-Memory-Computing (IMC) accelerator for Ternary Weight Neural Network (TWN) inference.  ... 
arXiv:2201.07634v1 fatcat:wtfbk5gjnzaw7mjjl37ehdf6p4

Table of contents

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Zeng 1109 MRIMA: An MRAM-Based In-Memory Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S. Angizi, Z. He, A. Awad, and D.  ...  FPGAs and Reconfigurable Systems An Extended Nonstrict Partially Ordered Set-Based Configurable Linear Sorter on FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  ... 
doi:10.1109/tcad.2020.2985607 fatcat:ppmomnva5bftfm5gb6szlo3gki

Interplay Bitwise Operation in Emerging MRAM for Efficient In-memory Computing

Hao Cai, Honglan Jiang, Yongliang Zhou, Menglin Han, Bo Liu
2020 CCF Transactions on High Performance Computing  
Considering the requirement of mixed-precision memory, we propose a novel write-only in-memory computing paradigm based on interplay bitwise operation in two terminal or three terminal MRAM bit-cell, which  ...  Four nonvolatile approximate full adders (AxFAs) are proposed and implemented in different MRAM bit-cells. The AxFAs can be easily reconfigured into memory units with simple connections.  ...  Figure 1 illustrates the block diagram of a MRAM based hybrid precision memory system.  ... 
doi:10.1007/s42514-020-00045-6 fatcat:4exo3z3lmraqnnoqvkc7c4wdiy

2020 Index IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Vol. 39

2020 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Cai, Y., +, TCAD July 2020 1414-1427 MRIMA: An MRAM-Based In-Memory Accelerator.  ...  ., +, TCAD Aug. 2020 1550-1554 Exposing Hardware Trojans in Embedded Platforms via Short-Term Aging. MRIMA: An MRAM-Based In-Memory Accelerator.  ... 
doi:10.1109/tcad.2021.3054536 fatcat:wsw3olpxzbeclenhex3f73qlw4