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MISE: Providing performance predictability and improving fairness in shared main memory systems

L. Subramanian, V. Seshadri, Yoongu Kim, B. Jaiyen, O. Mutlu
2013 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)  
Applications running concurrently on a multicore system interfere with each other at the main memory. This interference can slow down di erent applications di erently.  ...  maximum slowdown (i.e., unfairness) in the system.  ...  We acknowledge members of the SAFARI group for their feedback and for the stimulating research environment they provide.  ... 
doi:10.1109/hpca.2013.6522356 dblp:conf/hpca/SubramanianSKJM13 fatcat:25diebjownhvxorqqw7oafmifa

MISE: Providing Performance Predictability and Improving Fairness in Shared Main Memory Systems

Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu
2018
Applications running concurrently on a multicore system interfere with each other at the main memory. This interference can slow down different applications differently.  ...  maximum slowdown (i.e., unfairness) in the system.  ...  We acknowledge members of the SAFARI group for their feedback and for the stimulating research environment they provide.  ... 
doi:10.1184/r1/6469025.v1 fatcat:ama4ddbsfjbivbaasny2fudhyq

Mises, bastiat, public opinion, and public choice

Bryan Caplan, Edward Stringham
2005 Review of Political Economy  
We argue that Mises' and Bastiat's views in this area were both original and insightful.  ...  We argue that Mises' and Bastiat's views in this area were both original and insightful.  ...  " (1964a, p. 4) This does not mean that the hopes of Mises and Bastiat for improving economic literacy are in vain.  ... 
doi:10.1080/0953825042000313825 fatcat:2tutcakiwngyzoynnn4jq426iq

Predictable Performance and Fairness Through Accurate Slowdown Estimation in Shared Main Memory Systems [article]

Lavanya Subramanian, Vivek Seshadri, Yoongu Kim, Ben Jaiyen, Onur Mutlu
2018 arXiv   pre-print
Our goal is to accurately estimate application slowdowns, towards providing predictable performance.  ...  This paper summarizes the ideas and key concepts in MISE (Memory Interference-induced Slowdown Estimation), which was published in HPCA 2013 [97], and examines the work's significance and future potential  ...  This research was also partially supported by the NSF (grant 0953246), SRC, and Intel URO Memory Hierarchy Program.  ... 
arXiv:1805.05926v1 fatcat:ihxuzyer3ngz3p66o5c34c2ws4

Varieties of Entrepreneurial Function under Totalitarian (dis)Orders

Fernando D'Andrea, João Daniel Ruettimann
2019 Mises  
The real exercise of entrepreneurship defies the unreal socialist economic system in three basic ways: by exercising this latent entrepreneurial function in the most unfavorable conditions creating secondary  ...  markets in order to correct an official planned scarcity; by escaping the widespread statist mentality in socialist societies; and by actually exercising economic calculation in spite of the politburo  ...  Whilst life seeks out to create novel and improbable structures, post-totalitarian systems strive to cage it under more predictable and probable stages.  ... 
doi:10.30800/mises.2019.v7.1239 fatcat:nvl6iwrmibfpzinzk5gdfovwte

Providing High and Controllable Performance in Multicore Systems Through Shared Resource Management [article]

Lavanya Subramanian
2015 arXiv   pre-print
We propose and demonstrate several use cases of ASM that leverage it to provide soft performance guarantees and improve performance and fairness.  ...  We propose and demonstrate two use cases that can leverage MISE to provide soft performance guarantees and high overall performance/fairness.  ...  As a result, MISE-QoS is able to significantly improve the performance of the other applications in the system (as we show next). System Performance and Fairness.  ... 
arXiv:1508.03087v1 fatcat:ncmj4iqsonhxbnishe22rnecyq

John Maynard Keynes and Ludwig von Mises on Probability

Ludwig van den Hauwe
2021 Procesos de Mercado: revista europea de economia politica  
In particular it is argued that in some relevant respects Ludwig von Mises' interpretation of the concept of probability exhibits a closer affinity with the interpretation of probability developed by his  ...  Nevertheless the respective views of these authors with respect to the meaning and interpretation of probability exhibit a closer conceptual affinity than has been acknowledged in the literature.  ...  Once the mathematical theory has been set up in this way, we can deduce consequences from it by logic, and these provide predictions and explanations of further observable phenomena.  ... 
doi:10.52195/pm.v5i1.315 fatcat:cbh34evmtzfrtleuc3a3fdsofa

Recent Advances in Overcoming Bottlenecks in Memory Systems and Managing Memory Resources in GPU Systems [article]

Onur Mutlu, Saugata Ghose, Rachata Ausavarungnirun
2018 arXiv   pre-print
with growing memory densities and latencies; and (3) performance, programmability, and portability issues in modern GPUs, especially those related to memory system resources.  ...  This article features extended summaries and retrospectives of some of the recent research done by our research group, SAFARI, on (1) various critical problems in memory systems and (2) how memory system  ...  This work (1) develops a model called MISE, which predicts the impact of interference in DRAM on the overall system performance; and (2) uses this model to design new memory schedulers that improve fairness  ... 
arXiv:1805.06407v2 fatcat:vn5mju4fivgtjho7buv6pauaga

Research Problems and Opportunities in Memory Systems

2014 Supercomputing Frontiers and Innovations  
memory systems), 3) providing predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems).  ...  The memory system is a fundamental performance and energy bottleneck in almost all computing systems.  ...  Some of the research reported here was also partially supported by GSRC, Intel URO Memory Hierarchy Program, Intel Science and Technology Center on Cloud Computing, NIH, NSF, and SRC.  ... 
doi:10.14529/jsfi140302 fatcat:2zfa7zk3qjgohdsgxmkkqaamuu

HSM

Xia Zhao, Magnus Jahre, Lieven Eeckhout
2020 Proceedings of the Twenty-Fifth International Conference on Architectural Support for Programming Languages and Operating Systems  
improves system throughput (by 18.9% on average) compared to proportional SM partitioning while maintaining the QoS target for the high-priority application in challenging mixed memory/compute-bound multi-program  ...  In addition, we use HSM to guide various resource management schemes in multitasking GPUs: HSM-Fair significantly improves fairness (by 1.59× on average) compared to even partitioning, whereas HSM-QoS  ...  This work was supported in part by European Research Council (ERC) Advanced Grant agreement no. 741097, FWO projects G.0434.16N and G.0144.17N, NSFC under Grants no. 61572508, 61672526 and 61802427.  ... 
doi:10.1145/3373376.3378457 dblp:conf/asplos/0004JE20 fatcat:ecovkbgevzghzbil6rzxik2wfu

Main Memory Scaling: Challenges and Solution Directions [chapter]

Onur Mutlu
2015 More than Moore Technologies for Next Generation Computer Design  
predictable performance and QoS to applications sharing the memory system (i.e., QoS-aware memory systems).  ...  The memory system is a fundamental performance and energy bottleneck in almost all computing systems.  ...  Computing between 2010-2014, including invited talks at the 2011 International Symposium on Memory Management and ACM SIGPLAN Workshop on Memory System Performance and Correctness [89] and the 2012  ... 
doi:10.1007/978-1-4939-2163-8_6 fatcat:okw4kxakuja43kac65zy5c35ye

Aggregate Flow-Based Performance Fairness in CMPs

Zhonghai Lu, Yuan Yao
2016 ACM Transactions on Architecture and Code Optimization (TACO)  
mixtures and achieves nearly ideal performance fairness.  ...  Full-system evaluations in GEM5 demonstrate that, compared to classic packet-centric and latest application-prioritization approaches, our approach significantly improves weighted speed-up for all multi-application  ...  Then, new main memory request scheduling mechanisms exploiting MISE, MISE-QoS, and MISE-Fair are developed to provide soft QoS guarantees to one or more applications without compromising system performance  ... 
doi:10.1145/3014429 fatcat:af3dfjevqjclhd3ufmctpycy2e

Memory Access Scheduling Based on Dynamic Multilevel Priority in Shared DRAM Systems

Dongliang Xiong, Kai Huang, Xiaowen Jiang, Xiaolang Yan
2016 ACM Transactions on Architecture and Code Optimization (TACO)  
Interapplication interference at shared main memory severely degrades performance and increasing DRAM frequency calls for simple memory schedulers.  ...  The simulation results show that DMPS has 7.2% better system performance and 22% better fairness over FRFCFS at low hardware complexity and cost.  ...  ACKNOWLEDGMENTS The authors thank the anonymous reviewers for their valuable feedback, which immensely helped in improving the article.  ... 
doi:10.1145/3007647 fatcat:fv2px4ej3ncl3l7pbjrsptum4q

Techniques for Shared Resource Management in Systems with Throughput Processors [article]

Rachata Ausavarungnirun
2018 arXiv   pre-print
We propose changes to the memory controller design and its scheduling policy to mitigate inter-application interference in heterogeneous CPU-GPU systems.  ...  However, this success has been accompanied by new performance bottlenecks throughout the memory hierarchy of GPU-based systems.  ...  In addition to my family, I would like to thank my advisor, Prof. Onur Mutlu, for providing me with great research environment.  ... 
arXiv:1803.06958v1 fatcat:3mqbwegpkvdrpk6sqwb3ooyh7e

Symmetry-Agnostic Coordinated Management of the Memory Hierarchy in Multicore Systems

Miao Zhou, Yu Du, Bruce Childers, Daniel Mosse, Rami Melhem
2016 ACM Transactions on Architecture and Code Optimization (TACO)  
In a multicore system, many applications share the last-level cache (LLC) and memory bandwidth. These resources need to be carefully managed in a coordinated way to maximize performance.  ...  DRAM is still the technology of choice in most systems.  ...  Fairness of BA, WP, BA+WP, and MCRM normalized to SHARE on an asymmetric memory system. Fig. 8 . 8 Fig. 8.  ... 
doi:10.1145/2847254 fatcat:q4umjghjvngxrfazvbrx5tfyly
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