Filters








26 Hits in 10.3 sec

MIRA: A Multi-layered On-Chip Interconnect Router Architecture

Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das
2008 2008 International Symposium on Computer Architecture  
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology.  ...  The design is based on the concept of dividing a traditional 2D NoC router along with the rest of the on-chip communication fabric into multiple layers, with the objective of exploiting the benefits of  ...  In this paper, we propose the design of a multi-layered 3D NoC router architecture, called MIRA, for enhancing the performance, energy efficiency, and thermal behavior of on-chip interconnects.  ... 
doi:10.1109/isca.2008.13 dblp:conf/isca/ParkEDMXVD08 fatcat:cnkwp5pegjgu7juq4tgbykvj6q

MIRA

Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, N. Vijaykrishnan, Chita R. Das
2008 SIGARCH Computer Architecture News  
Recently, Network-on-Chip (NoC) architectures have gained popularity to address the interconnect delay problem for designing CMP / multi-core / SoC systems in deep sub-micron technology.  ...  The design is based on the concept of dividing a traditional 2D NoC router along with the rest of the on-chip communication fabric into multiple layers, with the objective of exploiting the benefits of  ...  In this paper, we propose the design of a multi-layered 3D NoC router architecture, called MIRA, for enhancing the performance, energy efficiency, and thermal behavior of on-chip interconnects.  ... 
doi:10.1145/1394608.1382143 fatcat:i6pxabrnz5eklhykeijbknhsfi

Design of TSV-Sharing Topologies for Cost-Effective 3D Networks-on-Chip

Poona Bahrebar, Dirk Stroobandt
2015 Proceedings of the 8th International Workshop on Network on Chip Architectures - NoCArc '15  
Thus, it is necessary to restrict the number of TSVs in order to design cost-effective 3D on-chip networks.  ...  Furthermore, the resulting architecture is no longer a mesh.  ...  As surveyed in [13] , the Xbar-connected Network-on-Tiers (XNoTs), Dimensionally-Decomposed (DimDe) router, and 3D MIRA are other classes of multi-layered topologies which were designed to make the best  ... 
doi:10.1145/2835512.2835514 dblp:conf/micro/BahrebarS15 fatcat:rk35pcizavhdzpdnnmrme5iwcq

NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures [article]

Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García-Oritz, Thilo Pionteck
2019 arXiv   pre-print
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip.  ...  Furthermore, we propose a high vertical-throughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers.  ...  Since the integration properties of any interconnect will differ if it spans multiple heterogeneous layers of a chip, heterogeneous 3D interconnects must account for this property.  ... 
arXiv:1909.04554v1 fatcat:betn22xflzcgvo7fyvzlk6a73i

Configurable Low-Latency Interconnect for Multi-core Clusters [chapter]

Giulia Beanato, Igor Loi, Giovanni De Micheli, Yusuf Leblebici, Luca Benini
2013 IFIP Advances in Information and Communication Technology  
In this chapter we propose a network architecture, 3D-LIN, based on 3D integration technology.  ...  The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest  ...  [15] propose a Multi-layered on-chip Interconnect Router Architecture (MIRA) divides the NoC between the multiple layers optimizing the micro-architecture for Non Uniform Cache Architecture (NUCA)-based  ... 
doi:10.1007/978-3-642-45073-0_6 fatcat:iojugyjte5ednehbxdnsee3scm

Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model

Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen
2011 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip - NOCS '11  
Three-Dimensional (3D) integration is a solution to the interconnect bottleneck in Two-Dimensional (2D) Multi-Processor System on Chip (MPSoC). 3D IC design improves performance and decreases power consumption  ...  by replacing long horizontal interconnects with shorter vertical ones.  ...  The on-chip network, considered for experiment is formed by a typical wormhole router structure including input buffers, a routing unit, a switch allocator and a crossbar.  ... 
doi:10.1145/1999946.1999958 dblp:conf/nocs/EbrahimiDLPT11 fatcat:5yfxxlwse5hkrnsi2mintcsb5e

D5.2: Best Practices for HPC Procurement and Infrastructure

Norbert Meyer, Marcin Lawenda
2013 Zenodo  
Specific areas of interest are analysed in depth in terms of the market they belong to and the general HPC landscape, with a particular emphasis on the European point of view.  ...  whole on the acquisition and hosting of HPC systems and infrastructure.  ...  Further development steps of the chips will require new materials, new architectures, and a new interconnect.  ... 
doi:10.5281/zenodo.6572412 fatcat:2bqftmr5zzb7na6pnlrlxxuqnu

Future trends in microelectronics - reflections on the road to nanotechnology

1997 Precision engineering  
This activity was motivated by the idea that a Si based fight emitting diode would enable mira-chip optical interconnects between logic gates, and thereby alleviate the so-called "interconnect bottleneck  ...  Consequently, when the whole CPU consists of only a single chip the on-chip wiring has to take over that communication burden which was carried by the package interconnections in earlier multi-chip processors  ...  Increasingly, the tendency is package several chips together in the form of multichip module, using techniques such as wire bonding, tape automated bonding and flip chip bonding to reduce the interconnections  ... 
doi:10.1016/0141-6359(97)90048-9 fatcat:j7blw4wn6zbitmoqqffj46g54e

Toxicity Analysis and Cry Gene Profiling of Bacillus Thuringiensis Isolated from Western Ghats of Tamil Nadu State, India

A. Ramalakshmi, P. Annakodi, V. Udayasurian, V. Balasubramani
2018 Proceedings of the Indian National Science Academy  
Computing as a discipline is a recent one even though the practice of using mechanical aids for calculation can have various dates based on the perspective of the reader like Blaise Pascal in 1600s, George  ...  The thesis, which had a far-reaching impact on this field, is informally stated below: Any algorithmic problem for which an algorithm can be found in any programming language on any computer (existing  ...  Chip Interconnection Chip interconnection has become an important issue in recent times. One can say that chip interconnection technology has made progress in discrete steps.  ... 
doi:10.16943/ptinsa/2018/49413 fatcat:2w6rohpbava5zh6m26tsiz7qky

NoCs in heterogeneous 3D SoCs : co-design of routing strategies and microarchitectures [article]

Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck, Universitäts- Und Landesbibliothek Sachsen-Anhalt, Martin-Luther Universität
2021
Heterogeneous 3D System-on-Chips (3D SoCs) are the most promising design paradigm to combine sensing and computing within a single chip.  ...  Furthermore, we propose a high vertical-throughput router microarchitecture that is adjusted to the routing algorithms and that fully overcomes the limitations of slower layers.  ...  His current research interests include network-on-chip communication architectures, especially for FPGA and heterogeneous 3D architecture.  ... 
doi:10.25673/36540 fatcat:digwtqewijfczf5tiqcdpdh4c4

Enabling In-situ Execution of Coupled Scientific Workflow on Multi-core Platform

Fan Zhang, Ciprian Docan, Manish Parashar, Scott Klasky, Norbert Podhorszki, Hasan Abbasi
2012 2012 IEEE 26th International Parallel and Distributed Processing Symposium  
In this paper, we investigate the in-situ execution of the coupled components of a scientific application workflow so as to maximize on-chip exchange of data.  ...  With the increasing performance gap between on-chip data sharing and off-chip data transfers in current systems based on multicore processors, moving large volumes of data using communication network fabric  ...  Mira and Sequoia will both employ the IBM Blue Gene/Q 18-core processor to exploit more on-chip parallelism.  ... 
doi:10.1109/ipdps.2012.122 dblp:conf/ipps/ZhangDPKPA12 fatcat:ve2blbfqp5bqjaw3wmmmogq3ky

D8.4: Final Report on Petascale Systems and Centre Assessment

Guillermo Aguirre, François Robin, Jean-Philippe Nominé, Marco Sbrighi
2012 Zenodo  
and expands the important work started in the PRACE Preparatory Phase project (PRACE-PP, January 2008 – June 2010), which sought to reach informed decisions within PRACE as a whole on the acquisition  ...  Task 1 - Assessment of petascale systems - has performed a continuous market watch and analysis of trends.  ...  Figure 7: Interconnect technologies in petascale systems Static analysis -Architecture All petascale systems make use of multi-core CPUs, and all except one of them utilize homogeneous cores (meaning  ... 
doi:10.5281/zenodo.6553025 fatcat:n6vcl4z4srapvl2usgepnvoqje

Tutorial: Parallel simulation on supercomputers

Kalyan S. Perumalla
2012 Proceedings Title: Proceedings of the 2012 Winter Simulation Conference (WSC)  
typical hardware and software characteristics of extant and emerging supercomputing platforms, and presents issues and solutions in executing large-scale parallel discrete-event simulation scenarios on  ...  Accordingly, the United States Government retains and the publisher, by accepting the article for publication, acknowledges that the United States Government retains a non-exclusive, paid-up, irrevocable  ...  operation on top of the point-to-point messaging of underlying communication layers.  ... 
doi:10.1109/wsc.2012.6465257 dblp:conf/wsc/Perumalla12 fatcat:yegivu4rxjh2xck3dg5bbf3rjm

Table of Contents – Technical

2021 2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium  
We also discuss the use of the new definitions in a multi-layer error detection and correction system. 11:25 A Comparative Study of On-Chip CMOS S&H Voltage Sensors for Power Integrity: SOI  ...  The FSS design is based on a three- layer structure. The first layer is a 3D printed lossy material, the second layer is an air gap, and the third layer is a ground plane.  ... 
doi:10.1109/emc/si/pi/emceurope52599.2021.9559379 fatcat:bqobkpurjje4vb5xpdk56r4lpi

A composable and predictable on-chip interconnect [article]

Hansson, MA (Andreas), Corporaal, H (Henk), Goossens, KGW (Kees)
2009
Although the problem can be mitigated by using a partial crossbar [128] , the key to architectural scalability is a distributed multi-hop interconnect. In a multi-hop interconnect, e.g.  ...  on the NI and router architecture.  ...  A.2.  ... 
doi:10.6100/ir642929 fatcat:rqwyl7jdcrac7cug2y77lq662m
« Previous Showing results 1 — 15 out of 26 results