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ME64 - A Parallel Hardware Architecture for Motion Estimation Implemented in FPGA [chapter]

Diogo Zandonai, Sergio Bampi, Marcel Bergerman
IFIP International Federation for Information Processing  
The results herein presented validate the ME64 against a software implementation, using an external I/O data driver. Hardware Architecture for Motion Estimation, Motion Estimation, Video Compression.  ...  This paper presents ME64, a dedicated scalable hardware architecture for fast computation of motion vectors.  ...  This is a common criterion in motion estimation hardware implementations [4] [6] [9] because it does not involve multiplications or divisions.  ... 
doi:10.1007/1-4020-8149-9_32 dblp:conf/ifip10-3/ZandonaiBB04 fatcat:tizz5li6rzdw5bkl7fno5w7hrq