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Low-power reliable SRAM cell for write/read operation

C. M. R. Prabhu, Ajay Kumar Singh
2014 IEICE Electronics Express  
In this paper, a low-power reliable (LPR) SRAM cell is proposed for minimizing the power consumption and to enhance the performance.  ...  Low power SRAM cell is a critical component in modern VLSI systems. The major portion of the power dissipation in the SRAM cell is due to large voltage swing on the bit lines during write operation.  ...  The proposed ZA [3] as well as low power 7T [4] SRAM cells are designed for power reduction in write '0' operation.  ... 
doi:10.1587/elex.11.20140913 fatcat:frpmzmj7vzccxpnpmer3x7kqru

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, Ching-Te Chuang
2010 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The test chip measurement results show that at 0.2 V V DD , an operation frequency of 6.0 MHz can be achieved with power consumption of 10.4 W. Index Terms-Low power, low voltage, single-ended SRAM.  ...  and operation speed of a single-ended read/write 8 T SRAM cell.  ...  ACKNOWLEDGMENT The authors are grateful to National Chip Implement Center (CIC), Taiwan, and United Microelectronics Corporation (UMC), Taiwan, for technology support.  ... 
doi:10.1109/tcsi.2010.2071690 fatcat:edhuaxhrunfnha3cgymgmu3shi

Dynamic Noise Margin Analysis of a Low Voltage Swing 8T SRAM Cell for Write Operation

P. Upadhyay, R. Kar, D. Mandal, S. P. Ghoshal
2013 International Journal of Signal Processing Systems  
Microwind 3.1 is used for simulation purpose.  Index Terms-CMOS, dynamic power, dynamic noise margin, pulse width, sram, voltage swing, word line  ...  The dynamic noise margin (DNM) analysis is carried out and the results are compared with those of conventional 6T SRAM cell and existing 10T SRAM cell for different word line pulse widths.  ...  For controlling the noise margin during write/read operations, the sizes of the transistors are a major concern.  ... 
doi:10.12720/ijsps.1.2.136-140 fatcat:4bef5hsuo5cd5f5bevp32znexa

Charge recycling 8T SRAM design for low voltage robust operation

Xu Wang, Chao Lu, Zhigang Mao
2016 AEU - International Journal of Electronics and Communications  
It is attractive to design power efficient and robust SRAM in low voltage and high performance systems for mobile or battery-powered electronics.  ...  In addition, two types of SRAM cells are employed to improve the robustness in write operation, and hierarchical bit-line structure is applied to reduce the power consumption in read operation.  ...  His current research interests include VLSI design methodology, high-speed digital circuit design technology, low power electronics, signal processor architecture, and hardware security technology and  ... 
doi:10.1016/j.aeue.2015.09.014 fatcat:2pb5nw74zzg3bocjmnpnaihbcq

Low Power SRAM with Boost Driver Generating Pulsed Word Line Voltage for Sub-1V Operation

Masaaki Iijima, Kayoko Seto, Masahiro Numa, Akira Tada, Takashi Ipposhi
2008 Journal of Computers  
Instability of SRAM memory cells derived from the process variation and lowered supply voltage has recently been posing significant design challenges for low power SoCs.  ...  Simulation results have shown that the proposed approach not only shortens the access time but mitigates the impact of V th variation on performance even at ultra low supply voltage less than 0.5 V.  ...  Hence, power management in SRAM operating at low power consumption is indispensable for future system LSI designs.  ... 
doi:10.4304/jcp.3.5.34-40 fatcat:uacs6fbzn5b2laubimbj3zuskm

Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up

Hraziia, Adam Makosiej, Giorgio Palma, Jean-Michel Portal, Marc Bocquet, Olivier Thomas, Fabien Clermidy, Marina Reyboz, Santhosh Onkaraiah, Christophe Muller, Damien Deleruyelle, Andrei Vladimirescu (+2 others)
2013 Solid-State Electronics  
It is shown that high R OFF /R ON is necessary to ensure reliable RECOVERY operation and high SRAM yield under cell area and power consumption constraints.  ...  Abstract This work presents a Non-Volatile SRAM (NV-SRAM) cell, resilient to information loss. The cell features fast storage (20ns) for the operating voltage of 1.0V.  ...  Control signals during different operation phases of the NV-SRAM cell Normal SRAM operation Normal SRAM operations (write/read) are not influenced by the presence of R 1 and R 2 as they are isolated  ... 
doi:10.1016/j.sse.2013.02.045 fatcat:iuedrxbxf5hunebjegoydh2qdu

Design and Analysis of 1-Bit SRAM

Ravi Hosamani, K.L.E. Institute of Technology, Hubli
2020 International Journal of Engineering Research and  
In this paper 6T SRAM cell circuit is designed for 1-Bit storage.  ...  It does not require refreshing periodically which makes it the most popular memory cell among VLSI designers. Hence continuous work is going on for the better performance of SRAM cells.  ...  RESULTS AND DISCUSSIONS The functionality write/read operation of 1x1 (1-Bit) 6T SRAM cell is shown in Fig. 10 . 1 - 101 Bit 6T SRAM Write/Read Operation TABLE I I . 2:4 DECODER TRUTH TABLE S0 S1  ... 
doi:10.17577/ijertv9is090130 fatcat:vubcjtrnn5cqpmfmsjop2pb4ti

Design And Analysis Of RHBD Memory Cells And 4x4 RHBD 10T Memory Cell Architecture

2019 VOLUME-8 ISSUE-10, AUGUST 2019, REGULAR ISSUE  
Depending on power, write/read time, the layout area of 14T, 12T and 10T RHBD memory cells and their performance on power for read/write operations are observed.  ...  This paper aims at is proposing an area efficient and high reliable RHBD memory cell for the above said application using 45nm technology in Cadence Tool.  ...  SRAMs were designed using reduced delay, area, power and reliability calculation in [1] .In general, SRAM cells are highly affected to reliability changes due to high densities, low critical charge and  ... 
doi:10.35940/ijitee.j9946.0881019 fatcat:ipaocq2uwvgydhvm2y3euficee

Design of highly reliable energy-efficient SEU tolerant 10T SRAM cell

C.I. Kumar, B. Anand
2018 Electronics Letters  
The parasitic extracted simulations show that by employing the proposed 10T-SRAM cell, an average improvement of ∼ 29, 5/10%, and 108/129%, in layout area, write/read access time (WAT/RAT), and write/read  ...  In 32 nm technology, the proposed SRAM cell shows 42/125% and 54/ 8%, in WSNM/RSNM and WAT/RAT, respectively, better results as compared with 10T SRAM cell at a supply voltage 0.3 V.  ...  Performance, power, and area comparisons: Table 1 compares the figures-of-merit (FOM) of area, power, write/read access time (WAT/RAT), and WSNMs/RSNMs of the proposed 10T-SRAM cell with those of 6 T  ... 
doi:10.1049/el.2018.7267 fatcat:ds7sffot2fgb7kckpx63ofobqq

Process Tolerant and Power Efficient SRAM Cell for Internet of Things Applications

T. G. Sargunam, Lim Way Soong, C. M. R. Prabhu, Ajay Kumar Singh
2022 Computers Materials & Continua  
47.75% for write and 35.59% and 36.56% for read operations compared to 6 T and 8 T SRAM cells.  ...  The cache memory designed on Static Random-Access Memory (SRAM) cell with features such as low power, high speed, and process tolerance are highly important for the IoT memory system.  ...  The authors would like to thank the editors of CMC and anonymous reviewers for their time and reviewing this manuscript.  ... 
doi:10.32604/cmc.2022.023452 fatcat:cv6zcu642vdhboepcbmq4lou34

Ultra low voltage and low power Static Random Access Memory design using average 6.5T technique

Nagalingam RAJESWARAN, Tenneti MADHU, Bini JOY, Ruth Anita SHIRLEY
2015 Leonardo Electronic Journal of Practices and Technologies  
With reduced supply voltage, SRAM cell design will go through severe stability issues. In this paper, we present a highly stable average nT SRAM cell for ultra-low power in 125nm technology.  ...  An average 6.5T SRAM and average 8T SRAM are designed and compared with 6T SRAM, 8T SRAM, 9T SRAM, 10T SRAM and 14T SRAM cells.  ...  153 software and the parameters such as power consumption and delay time are determined. Based on the results obtained proposed method has better performance and it is used to build the memory block.  ... 
doaj:5f48f794a0d848d8a746d3c086a0a311 fatcat:ohqfnxancvf6dals6cinmjlrqm

Design and Analysis of Transient Fault Tolerance in SRAM with different NT Techniques

S. Ravichand, T. Madhu, M. Sailaja
2016 International Journal of Computer Applications  
CELLThe basic architecture of the proposed write read decoupled SRAM block illustrated inFig.8.  ...  The significant improvements obtained in the results through the use of 10T cell which will be applicable for future low power memory design.  ... 
doi:10.5120/ijca2016911694 fatcat:mx4fujz3sfgspdmdhy5ofxnnym

Accelerating Bulk Bit-Wise X(N)OR Operation in Processing-in-DRAM Platform [article]

Shaahin Angizi, Deliang Fan
2019 arXiv   pre-print
The simulation results show that DRIM achieves on average 71x and 8.4x higher throughput for performing bulk bit-wise X(N)OR-based operations compared with CPU and GPU, respectively.  ...  DRIM uses the analog operation of DRAM sub-arrays and elevates it to implement bit-wise X(N)OR operation between operands stored in the same bit-line, based on a new dual-row activation mechanism with  ...  •Write/Read Operation: At initial state, both BL and BL is always set to V dd 2 .  ... 
arXiv:1904.05782v1 fatcat:imkzuky2ardgfeiune2up4kema

Robust 6T Si tunneling transistor SRAM design

Xuebei Yang, Kartik Mohanram
2011 2011 Design, Automation & Test in Europe  
SRAMs based on tunneling field effect transistors (TFETs) consume very low static power, but the unidirectional conduction inherent to TFETs calls for special care when designing the SRAM cell.  ...  Further, it not only has comparable performance and reliability to the 32nm 6T CMOS SRAM, but also consumes 6-7 orders of magnitude lower static power, making it attractive for low-power high-density SRAM  ...  Our second contribution addresses the limitation imposed by the unidirectional conduction property and improves write/read reliability of the 6T TFET SRAM.  ... 
doi:10.1109/date.2011.5763126 dblp:conf/date/YangM11 fatcat:ui7vnrmqxbg35d43trqsxjbz6y

DESIGN OF LOW POWER 8T SRAM WITH SCHMITT TRIGGER LOGIC

A. KISHORE KUMAR, D. SOMASUNDARESWARI, V. DURAISAMY, T. SHUNBAGA PRADEEPA
2014 Journal of Engineering Science and Technology  
Static Random Access Memory (SRAM) has become a key element in modern VLSI systems. In this paper, a low power design of 8 Transistor SRAM cell with Schmitt Trigger (ST) logic is proposed.  ...  The main intention of this paper is to design a new SRAM cell architecture to reduce the power consumption during both read / write operations and to improve SRAM access stability.  ...  The proposed design consumes less power than conventional 6T, 7T SRAM and adiabatic SRAM during write/read operation, reported in Table 3 .  ... 
doaj:1e3acf1e435b4d5aa7a077c0dd4b2487 fatcat:ags2eskcynewtj2qns7no4fm7m
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