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Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard

Junho Cho, Naresh R. Shanbhag, Wonyong Sung
2009 2009 IEEE Workshop on Signal Processing Systems  
Flexible and scalable LDPC decoder architecture is developed for the IEEE 802.11n standard.  ...  By applying these techniques, power saving of up to 35% is demonstrated when implemented in a 90nm CMOS technology.  ...  In this paper, flexible serial-parallel LDPC decoder architecture is designed for IEEE 802.11n standard, which defines the specification for enhanced high-throughput wireless local area network (WLAN)  ... 
doi:10.1109/sips.2009.5336223 dblp:conf/sips/ChoSS09 fatcat:rvz5wkcbgnh7ln5gfwnqknwzza

Low-power design of variable block-size LDPC decoder using nanometer technology

Chih-Hung Lin, Alex Chien-Lin Huang, Robert Chen-Hao Chang, Kuang-Hao Lin
2010 Proceedings of 2010 IEEE International Symposium on Circuits and Systems  
1 Abstract-This paper presents a low-power, variable blocksize and irregular LDPC decoding.  ...  Compared to recent state-of-the-art architectures, the proposed variable block-size LDPC decoder has 450 MHz clock frequency, 349.48 K gate counts, 168 mW power dissipation, and 1.215 Gbps throughput.  ...  The throughput value can meet the requirement of IEEE 802.11n standard. IV.  ... 
doi:10.1109/iscas.2010.5537590 dblp:conf/iscas/LinHCL10 fatcat:suubrtlezzfjfjique444xejiu

Comparison of Polar Decoders with Existing Low-Density Parity-Check and Turbo Decoders

Alexios Balatsoukas-Stimming, Pascal Giard, Andreas Burg
2017 2017 IEEE Wireless Communications and Networking Conference Workshops (WCNCW)  
Towards this end, in this paper, we perform a comparison of polar decoders against LDPC and Turbo decoders that are used in existing communications standards.  ...  the hardware implementation of polar decoders.  ...  ACKNOWLEDGEMENT The authors would like to thank Huawei Technologies for financial support.  ... 
doi:10.1109/wcncw.2017.7919106 dblp:conf/wcnc/Balatsoukas-Stimming17 fatcat:ds4fwpbiszdh3ddg6lquavhx2i

Fully Parallel Architecture of QC-LDPC Decoder for IEEE 802.11n Application

2020 International journal of recent technology and engineering  
The VLSI implementation of LDPC decoder is a big challenge.  ...  The Fully parallel architecture of the LDPC decoder for IEEE 802.11n standard using Min Sum decoding algorithm (MSA)has been designed.  ...  LDPC DECODER FOR IEEE 802.11N A fully parallel decoder architecture for a Quasi Cyclic(QC)LDPC decoder for standard IEEE 802.11n for the code rate of ½ and the block length of 648 bits is synthesized on  ... 
doi:10.35940/ijrte.a2314.059120 fatcat:b5okkkiatjcjfc7c52ayxca6z4

Reduced Complexity Quasi-Cyclic LDPC Encoder for IEEE 802.11N

Monica Mankar, Gajendra Asutkar, Pravin Dakhole
2016 International Journal of VLSI Design & Communication Systems  
In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC) encoder hardware based on Richardson and Urbanke lower-triangular algorithm for IEEE 802.11n wireless LAN Standard  ...  Proposed architecture of QC-LDPC encoder will be compatible for high-speed applications.  ...  The proposed architecture focuses Low complexity and high throughput for IEEE 802.11n standard.  ... 
doi:10.5121/vlsic.2016.7604 fatcat:xslppi6xkzc3vp6stsjjmdqckm

A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

C Roth, P Meinerzhagen, C Studer, A Burg
2010 2010 IEEE Asian Solid-State Circuits Conference  
We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard.  ...  The corresponding 90 nm CMOS ASIC has a core area of 1.77 mm 2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations.  ...  Felber for their support during ASIC design and testing. The presented work was kindly supported by the Hasler Foundation and the Swiss National Science Foundation.  ... 
doi:10.1109/asscc.2010.5716618 fatcat:opdu5b5lxbhzzbuk27uahk555e

Low Complexity LDPC Code Decoders for Next Generation Standards

T. Brack, M. Alles, T. Lehnigk-Emden, F. Kienle, N. Wehn, N. E. L'Insalata, F. Rossi, M. Rovini, L. Fanucci
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n), WiMax (IEEE802.16e) and DVB-S2 standards.  ...  According to this search state-of-the-art techniques for a low complexity design have been adopted in order to meet feasible high throughput decoder implementations.  ...  Acknowledgments Our special thanks goes to Friedbert Berens from the Computer Peripheral Group of STMicroelectronics, Geneva, Switzerland, for many valuable discussions.  ... 
doi:10.1109/date.2007.364613 dblp:conf/date/BrackALKWLRRF07 fatcat:vfjh3kv5urd3bowqf4q7zjrmwq

A massively parallel implementation of QC-LDPC decoder on GPU

Guohui Wang, Michael Wu, Yang Sun, Joseph R. Cavallaro
2011 2011 IEEE 9th Symposium on Application Specific Processors (SASP)  
As a case study, we present a GPU-based implementation of a real-world digital signal processing (DSP) application: low-density parity-check (LDPC) decoder.  ...  Experimental results show that the proposed GPU-based LDPC decoding accelerator can take advantage of the multi-core computational power provided by GPU and achieve high throughput up to 100.3Mbps.  ...  This class of codes are widely used in many wireless standards such as WiMax (IEEE 802.16e), WiFi (IEEE 802.11n) and high speed magnetic storage devices.  ... 
doi:10.1109/sasp.2011.5941084 dblp:conf/sasp/WangWSC11 fatcat:qvbd3xflmnfbpiooujfl64gyea

Matrix Merging Scheme and Efficient Decoding Techniques for Reconfigurable QC-LDPC Decoders

Min-An Chao, Xin-Yu Shih, An-Yeu Wu
2011 Journal of Signal Processing Systems  
Finally, to verify our design approach, we implement a triple-mode LDPC decoder chip which is compatible to IEEE 802.11n standard by using UMC 90 nm CMOS technology.  ...  The prototyping chip not only validates the proposed approach, but also outperforms the state-of-the-art QC-LDPC decoders for IEEE 802.11n systems.  ...  The authors would like to thank Yu-Hsin Chen and Yi-Ju Chen for simulation codes of the adaptive early termination, Jen-Yang Wen for partial RTL coding of the triple-mode LDPC decoder design as well as  ... 
doi:10.1007/s11265-011-0597-7 fatcat:c6vjj4jkpnhxxdavkdydfl2wr4

A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards

Yang Sun, Joseph R. Cavallaro
2008 2008 IEEE International SOC Conference  
In this paper we present an efficient system-onchip implementation of a 1-Gbps LDPC decoder for 4G (or beyond 3G) wireless standards.  ...  We utilize a pipelined version of the layered belief propagation algorithm to achieve partial-parallel decoding of structured LDPC codes.  ...  CONCLUSION A high performance LDPC decoder has been described that achieves a throughput of 1 Gbps.  ... 
doi:10.1109/socc.2008.4641546 dblp:conf/socc/SunC08 fatcat:uhbkjhnv5na3vmxaxhks2s4niu

Refresh-free dynamic standard-cell based memories: Application to a QC-LDPC decoder

Pascal Meinerzhagen, Andrea Bonetti, Georgios Karakonstantis, Christoph Roth, Frank Giirkaynak, Andreas Burg
2015 2015 IEEE International Symposium on Circuits and Systems (ISCAS)  
The low-power LDPC decoder architecture with refreshfree D-SCMs was implemented in a 90 nm CMOS process, and silicon measurements show full functionality and an information bit throughput of up to 600  ...  Mbps (as required by the IEEE 802.11n standard).  ...  IEEE 802.11n or the WiMAX standards.  ... 
doi:10.1109/iscas.2015.7168911 dblp:conf/iscas/MeinerzhagenBKR15 fatcat:kyrmp66ob5bkvdit6ovpu5xadi

Implementation of a multi-rate and multi-size LDPC decoder

Bing Li, Duo-jin Chen, Jun Xiong, Mei-qiang Shi
2009 IEICE Electronics Express  
A fully reconfigurable architecture of a LDPC (lowdensity parity check) decoder for IEEE 802.11n system is proposed in this paper.  ...  Furthermore, the proposed decoder also able to support multi-rate and multi-size LDPC codes decoding. The proposed decoder was implemented in UMC 0.18 μm CMOS technology.  ...  Introduction Due to LDPC's near Shannon limit performance, It has been adopted for several industrial standards, such as DVB-S2, WMAN(IEEE 802.16e) and WLAN(IEEE 802.11n) [1] .  ... 
doi:10.1587/elex.6.1509 fatcat:kfpnlzhzrrcd7l22usu67q7do4

Trends and challenges in LDPC hardware decoders

Tinoosh Mohsenin, Bevan Baas
2009 2009 Conference Record of the Forty-Third Asilomar Conference on Signals, Systems and Computers  
This paper provides an overview of current research in LDPC decoder algorithms and architectures that are well suited for hardware implementations.  ...  Near and long-term trends of next generation LDPC requirements are made and an analysis of how current architectures will fare with the increasing demands on throughput, BER performance, power dissipation  ...  Although there is no standard for magnetic recording hard disks, they demand high code rate, low error floor, and high decoding throughput (e.g., rate-8/9 LDPC decoder with 2.1 Gbps throughput [5] ).  ... 
doi:10.1109/acssc.2009.5469947 fatcat:lqyd7x4txfginm3qcfehqz4vhm

VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

Yang Sun, Marjan Karkooti, Joseph R. Cavallaro
2007 2007 IEEE International Symposium on Circuits and Systems  
A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented.  ...  The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes.  ...  To balance the implementation complexity and the decoding throughput, a structured QC-LDPC code was proposed in [4] recently for modern wireless communication systems including but not limited to IEEE  ... 
doi:10.1109/iscas.2007.378514 dblp:conf/iscas/SunKC07 fatcat:73recz7iajcspiwfiymp44jlyq

Flexible Radio Design: Trends and Challenges in Digital Baseband Implementation

Guido Masera, Amer Baghdadi, Frank Kienle, Christophe Moy
2012 VLSI design (Print)  
Condo provide a rich overview of state-of-the-art decoders able to deal with multiple LDPC codes adopted in communication standards such as DVB-S2, IEEE 802.11n (WiFi), IEEE 802.3an (10GBASE-T), and IEEE  ...  Fourth-generation communications systems call for a high amount of computational power due to multiantenna and multimode features.  ... 
doi:10.1155/2012/549768 fatcat:5ccwu7xpybe7ha5n5len5hlftm
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