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Low-power digital CDMA receiver
2003
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC
The advanced design task of the digital CDMA receiver are presented in this report. A biased number system and architecture is used to reduce the switching activity to reduce power consumption. ...
The CDMA Receiver receives the transmitted data from Transmitter and then it decodes the signal and extracts one preferable datum. ...
I Introduction Fig.1 shows an CDMA communication system. It consists of Transmitter and Receiver. The task of this design is to design the Receiver. ...
doi:10.1145/1119772.1119901
dblp:conf/aspdac/LiuCTJ03
fatcat:jzc76vb6ovguvmmnjhh3idxxge
Low-power digital CDMA receiver
Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003.
The advanced design task of the digital CDMA receiver are presented in this report. A biased number system and architecture is used to reduce the switching activity to reduce power consumption. ...
The CDMA Receiver receives the transmitted data from Transmitter and then it decodes the signal and extracts one preferable datum. ...
I Introduction Fig.1 shows an CDMA communication system. It consists of Transmitter and Receiver. The task of this design is to design the Receiver. ...
doi:10.1109/aspdac.2003.1195088
fatcat:2ilaxah3ijablit3ztpnfuyjee
A Clock-Harvesting Receiver Using 3G CDMA Signals in the 1900-MHz Band
2012
IEEE Transactions on Circuits and Systems - II - Express Briefs
The energy-detection-based receiver was fabricated in 0.13-μm CMOS and designed for low-power heavily duty-cycled operation. ...
Index Terms-Analog integrated circuits, code-division multiple access (CDMA), clock-harvesting receiver (CRX), synchronization, wake-up receiver (WRX), wireless sensor networks (WSNs). ...
In addition, the receiver must be designed with a low-power sleep state that does not dominate the timer power. ...
doi:10.1109/tcsii.2012.2218397
fatcat:2odb4s2sajf7vclg2s4m4ofd3u
Experimental Demonstration of a Radio on Free Space Optics System for Ubiquitous Wireless
2009
PIERS Online
We have evaluated this new DWDM RoFSO system by conducting field experiments in simultaneous transmission of various kinds of wireless services; for example, 3GPP cellular, WLAN, terrestrial digital broadcasting ...
Using a post EDFA the required received optical power can be even as low as −25 dBm and −20 dBm and still satisfy the 3GPP specification for W-CDMA signal transmission at 5 MHz and 10 MHz offsets respectively ...
A signal generator (Agilent E4438C) is used to generate a test signal (W-CDMA Test Model 1) with a signal power of −20 dBm which is transmitted over the RoFSO link and at the receiver side a digital mobile ...
doi:10.2529/piers080907022238
fatcat:ahhvt4lm5nahblys7qcybq2czu
RF/wireless interconnect for inter- and intra-chip communications
2001
Proceedings of the IEEE
Unlike the traditional "passive" metal interconnect, the "active" RF/wireless interconnect is based on low loss and dispersion-free microwave signal transmission, near-field capacitive coupling, and modern ...
It is also noted that the power consumption of output stage, which is usually determined by the receiver sensitivity, does not scale as the digital circuitry. ...
Let us assume the transmitted power of each being well controlled and all signals are received at with an equal power. ...
doi:10.1109/5.920578
fatcat:p2ig5gk4cvbercql4iyaly5eju
Wavelet based multicarrier CDMA system
2019
International Journal of Electrical and Computer Engineering (IJECE)
Emerging demands for high data rate services, high user capacity and low power consumption systems are the key driving forces behind the continued technology evolution in wireless communications. ...
Multicarrier CDMA is a wireless communication system that can be seen as a combination of direct sequence CDMA and Orthogonal Frequency Division Multiplexing techniques. ...
, i.e. when the time domain signal traverses from a low instantaneous power waveform to a high power waveform, it results in a high out of band distortion power, unless the transmitter's power amplifier ...
doi:10.11591/ijece.v9i4.pp3051-3059
fatcat:5gy6fecrdvdkhpiytthghvbqce
Overview Of MC CDMA Papr Reduction Techniques
2012
International Journal of Distributed and Parallel systems
To reduce PAPR the constraints are low power consumption, and low Bit Error Rate (BER). Spectral bandwidth is improved by better spectral characteristics, and low complexity/cost. ...
Code Division Multiple Access (MC CDMA) systems, due to large number of subcarriers. ...
The PAPR brings disadvantages like the design complexity of Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC).It also reduces power efficiency, increase BER and consumption of power ...
doi:10.5121/ijdps.2012.3217
fatcat:tfmvjw4wwzcsfatrhcxipmuury
FPGA Implementation of Low Complexity VLSI Architecture for DS-CDMA Communication System
2012
International Journal of Computer Applications
The paper also describes modulation and demodulation circuits for CDMA. ...
CDMA communication system easily meets these requirements of cellular communications. The design of the relevant circuits is based on CDMA approach of direct sequence spread spectrum technology. ...
The modulation reduces the high power density of the original data to a low level. ...
doi:10.5120/5818-8130
fatcat:4uc36fg37ffevmjtcmjalisdvy
Low power Multicarrier- Code Division Multiple Access Receiver on Field Programmable Gate Array
2019
International Journal of Advanced Trends in Computer Science and Engineering
The first objective of this paper is to design and verify a low power MC-CDMA receiver and the second objective is to implement the MC-CDMA receiver on FPGA. ...
This paper presents a low power multi-carrier code division multiple access (MC-CDMA) receiver on field-programable gate array (FPGA). ...
In conclusion, low power MC-CDMA receiver is successfully designed and implemented on FPGA. ...
doi:10.30534/ijatcse/2019/4781.62019
fatcat:6egwmuls7vefzcw3qrhupvfagy
CDMA Transmitter and Receiver Implementation Using FPGA
2013
IOSR Journal of Electronics and Communication Engineering
With CDMA, the narrow band message (typically digitized voice data) is multiplied by a large bandwidth signal that is a pseudo random noise code (PN code). ...
As different CDMA users take different PN sequences, each CDMA receiver can discriminate and detect its own signal, by regarding the signals transmitted by other users as noise-like interferences. ...
This is necessary due to the low power spectral density of DS-CDMA signals and it is only possible to detect the information bits after correlation. ...
doi:10.9790/2834-0725158
fatcat:qcgtfpwknba5bhmiupm5wshht4
VHDL Implementation of MAC based DSSS-CDMA Protocol for Solving near Far Effect IN Ad-hoc Network
2013
International Journal of Computer Applications
The aim is that, use "VHDL implementation" for MAC Based DSSS CDMA design, which consist transmitter & receiver with MAC protocol of a Ad-hoc network, which prevent fast degradation of network throughput ...
There are two solutions available for reducing this near far effect, first is Power control and second is Medium access problem. ...
In below figure this result is present when an interfering transmitter is much closer to the receiver than the intended and B is very low, the correlation &collision between the received signal from the ...
doi:10.5120/12098-8302
fatcat:yrn5wjvvjbg3faafcuoqtz4a7u
2005 Index
2005
IEEE Transactions on Vehicular Technology
Yugang Zhou, + , T-VT Mar 05
629-638
Analog-digital conversion
low power, low rate, wireless systs., UWB transceiver archit. ...
., + , T-VT Sep 05 1739-1746 low power, low rate, wireless systs., UWB transceiver archit. ...
Hyun-Jin Lee, + , T-VT Jul 05 1438-1446 CDMA cellular nets., pilot interf. cancellation technol. ...
doi:10.1109/tvt.2005.863647
fatcat:7ftwl4fyt5adfatoufxaoldhai
FPGA implementation of DS-CDMA Transmitter and Receiver
2018
International Journal of Reconfigurable and Embedded Systems (IJRES)
In this project direct sequence spread spectrum principle based code division multiple access (CDMA) transmitter and receiver is implemented on SPARTAN 3E FPGA. ...
The Xilinx synthesis technology (XST) of Xilinx ISE tool used for synthesis of transmitter and receiver on FPGA Spartan 3E. ...
Figure 10 shows DS CDMA top level RTL schematic. Figure 11 shows DS CDMA power report. ...
doi:10.11591/ijres.v6.i3.pp179-185
fatcat:56u24sp7obgtbd2zysqqf26qmq
Design of a cdma-based wireless data transmitter for embedded sensing
2002
IEEE Transactions on Instrumentation and Measurement
Index Terms-Code division multiple access (CDMA), embedded sensing, wireless data transmission. Robert X. Gao (M'91-SM'00) received the M.S. and Ph.D. degrees from the ...
This paper presents the design and prototype realization of a digital wireless data transmitter based on the code division multiple access technique. ...
CONCLUSION A compact, low-power digital wireless data transmitter based on the CDMA-coding technique has been designed, simulated, prototyped, and experimentally tested. ...
doi:10.1109/tim.2002.808020
fatcat:ezplzfhkfbapxprqx4ey6axmxm
Peak to Average Power Ratio Reduction in Mc Cdma System by Using Pulse Shaping Technique
2013
IOSR Journal of Electronics and Communication Engineering
One of the drawback of multicarrier code division multiple access (MC CDMA) is the high peak to average power ratio (PAPR). ...
Here three different pulse shaping filters (Raised cosine, Sinc power pulse and Nyqist pulse) are described for PAPR reduction in MC CDMA system. ...
They presents a novel MCCDMA which has low peak to average power ratio (PAPR). ...
doi:10.9790/2834-0722327
fatcat:cnpvo5ot7bcvhnll3jlj32cuee
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