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A multi-core-based heterogeneous parallel turbo decoder

Jianmin Zeng, Chubin Wu, Zhang Zhang, Xin Cheng, Guangjun Xie, Jun Han, Xiaoyang Zeng, Zhiyi Yu
2017 IEICE Electronics Express  
In this paper, we present a heterogeneous and highly reconfigurable parallel turbo decoder for LTE by employing a multi-core processor platform.  ...  A modified sliding-window algorithm is proposed to fully exploit the parallelism of turbo decoder, and a SIMD hardware module is designed for the multi-core processor to accelerate the decoding process  ...  Turbo decoders are usually implemented through Application Specific Integrated Circuit (ASIC) for reaching high-throughput and low-latency.  ... 
doi:10.1587/elex.14.20170768 fatcat:x2aqxwic3fejppmx4rykgvceti

A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi - core Processor

Chaolong ZHANG, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China, Zhekun HU, Jie Chen, The 709th Research In stitute of China Shipbuilding Industry Corporation, Wuhan 430009, China, Institute of Microelectronics , Chinese Academy of Sciences, Beijing 10029, China
2014 Journal of Engineering Science and Technology Review  
A network on chip (NOC) multi-core processor based on message-passing programming model is designed to implement the LTE-A turbo decoder in a parallel mode using pure Software Defined Radio (SDR) approach  ...  According to the features of the NOC multi-core processor, the implementation of turbo decoder is optimized to reduce the computational complexity and to increase the parallelization.  ...  Acknowledgements This work was financially supported by the National Natural Science Foundation of China (No. 61201265, No. 61221004 and No. 61376027). ______________________________ References  ... 
doi:10.25103/jestr.071.09 fatcat:whr5ppbtizdl7fizmhpr6ebhou

HSPA;/LTE-A turbo decoder on GPU and multicore CPU

Michael Wu, Guohui Wang, Bei Yin, Christoph Studer, Joseph R. Cavallaro
2013 2013 Asilomar Conference on Signals, Systems and Computers  
This paper compares two implementations of reconfigurable and high-throughput turbo decoders.  ...  Both implementations support max-log-MAP and log-MAP turbo decoding algorithms, various code rates, different interleaver types, and all block-lengths, as specified by HSPA+ and LTE-Advanced.  ...  TURBO DECODER IMPLEMENTATIONS At a high level, both the Ivy-Bridge and Nvidia Kepler architectures can be viewed as multi-core SIMD processors.  ... 
doi:10.1109/acssc.2013.6810402 dblp:conf/acssc/WuWYSC13 fatcat:whqyeveyu5fsfdrixn6tl2zhsu

A reconfigurable application specific instruction set processor for convolutional and turbo decoding in a SDR environment

Timo Vogt, Norbert Wehn
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Simulation results for Viterbi and turbo decoding demonstrate maximum throughput of 196 and 34 Mbps, respectively, and outperforms existing SDR based approaches for channel decoding.  ...  It features binary convolutional decoding, and turbo decoding for binary as well as duobinary turbo codes for all current and upcoming standards.  ...  and generator polynomials, • rate flexibility by internal depuncturing of punctured codes, • high throughput, low latency.  ... 
doi:10.1145/1403375.1403388 fatcat:pd32pb2kxrgy7pi3i7wcflkyeu

Guest Editorial

Myung Hoon Sunwoo
2011 Journal of Signal Processing Systems  
The next two papers focus on the design of a Turbo decoder for multi-standards and a BCH decoder for 100Gb/s optical communications.  ...  "Implementation of a Radix-4, Parallel Turbo Decoder and Enabling the Multi-Standard Support," by Rizwan Asghar et al. offers a unified architecture supporting radix-4 turbo decoders for multiple standards  ...  The next two papers focus on the design of a Turbo decoder for multi-standards and a BCH decoder for 100Gb/s optical communications.  ... 
doi:10.1007/s11265-011-0632-8 fatcat:jnqvjozy6bhqddg56nyorf6ld4

ASIP-Based Multiprocessor SoC Design for Simple and Double Binary Turbo Decoding

O. Muller, A. Baghdadi, M. Jezequel
2006 Proceedings of the Design Automation & Test in Europe Conference  
This paper presents a new multiprocessor platform for high throughput turbo decoding.  ...  These multiprocessor architectures benefit from the recent shuffling technique introduced in the turbo-decoding field to reduce communication latency.  ...  flexibility and scalability thanks to an adequate packet switching communication network. Other experiments and evaluations are being conducted on the proposed architecture model.  ... 
doi:10.1109/date.2006.244126 dblp:conf/date/MullerBJ06 fatcat:7a6wiaw2nveuvflvmhuao4bvei

Energy consumption analysis of software polar decoders on low power processors

Adrien Cassagne, Olivier Aumage, Camille Leroux, Denis Barthou, Bertrand Le Gal
2016 2016 24th European Signal Processing Conference (EUSIPCO)  
This fully generic SC decoder is used to perform comparisons of the different configurations in terms of throughput, latency and energy consumption.  ...  A N=4096 code length, rate 1/2 software SC decoder consumes only 14 nJ per bit on an ARM Cortex-A57 core, while achieving 65 Mbps.  ...  The low-power general purpose ARM32 and ARM64 processor test-beds based on big.LITTLE architecture are selected as representative of modern multi-core and heterogeneous architectures.  ... 
doi:10.1109/eusipco.2016.7760327 dblp:conf/eusipco/CassagneALBG16 fatcat:ozz4wpazofftligx4ny6dkbbta

System architecture for 3GPP LTE modem using a programmable baseband processor

Di Wu, Johan Eilert, Dake Liu, Anders Nilsson, Eric Tell, Erik Alfredsson
2009 2009 International Symposium on System-on-Chip  
The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ.  ...  This paper presents the system architecture of an LTE modem based on a programmable baseband processor.  ...  high-throughput forward error correction (FEC) decoding.  ... 
doi:10.1109/socc.2009.5335662 dblp:conf/issoc/WuELNTA09 fatcat:vrjjfrpwxfex7epmiumfpsk3gq

System Architecture for 3GPP-LTE Modem using a Programmable Baseband Processor

Di Wu, Johan Eilert, Rizwan Asghar, Dake Liu, Anders Nilsson, Eric Tell, Eric Alfredsson
2010 International Journal of Embedded and Real-Time Communication Systems  
The throughput and latency requirements of a Category 4 User Equipment (CAT4 UE) is met by adding a MIMO symbol detector and a parallel Turbo decoder supporting H-ARQ.  ...  This paper presents the system architecture of an LTE modem based on a programmable baseband processor.  ...  high-throughput forward error correction (FEC) decoding.  ... 
doi:10.4018/jertcs.2010070103 fatcat:ewcrun3tmnboxobmasadsh3qnu

Using Graphics Processing Units in an LTE Base Station

Qi Zheng, Yajing Chen, Hyunseok Lee, Ronald Dreslinski, Chaitali Chakrabarti, Achilleas Anastasopoulos, Scott Mahlke, Trevor Mudge
2014 Journal of Signal Processing Systems  
We also study the mapping method of key kernels onto a multi-GPU system to minimize the number of required GPUs and the overall subframe processing latency.  ...  GPUs are attractive because they are widely used massively parallel devices that can be programmed in a high level language.  ...  Acknowledgments We wish to thank Nilmini Abeyratne and Yuan Lin for their generous help and useful feedback on the paper.  ... 
doi:10.1007/s11265-014-0932-x fatcat:q6sxgnnygrcehhfdeizgkl7jiy

Application-Specific Accelerators for Communications [chapter]

Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro
2013 Handbook of Signal Processing Systems  
error correction codes (Viterbi, Turbo, LDPC) decoders.  ...  The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power.  ...  Fig. 26 26 Fig. 26 Turbo decoder accelerator architecture. Multiple MAP decoders are used to support high throughput decoding of Turbo codes.  ... 
doi:10.1007/978-1-4614-6859-2_23 fatcat:totrkiocljf4ni72xbsgboybdm

Application-Specific Accelerators for Communications [chapter]

Yang Sun, Kiarash Amiri, Michael Brogioli, Joseph R. Cavallaro
2010 Handbook of Signal Processing Systems  
error correction codes (Viterbi, Turbo, LDPC) decoders.  ...  The accelerators that we consider are mostly coarse grain to better deal with streaming data transfer for achieving both high performance and low power.  ...  Fig. 26 26 Fig. 26 Turbo decoder accelerator architecture. Multiple MAP decoders are used to support high throughput decoding of Turbo codes.  ... 
doi:10.1007/978-1-4419-6345-1_13 fatcat:bgppdcjc5zafdd4q2bwinepy2a

Implementation of a High Throughput 3GPP Turbo Decoder on GPU

Michael Wu, Yang Sun, Guohui Wang, Joseph R. Cavallaro
2011 Journal of Signal Processing Systems  
To improve efficiency of the decoder in the high SNR regime, we also present a low complexity early termination scheme based on average extrinsic LLR statistics.  ...  To fully utilize the computational resources on GPU, our decoder can decode multiple codewords simultaneously, divide the workload for a single codeword across multiple cores, and pack multiple codewords  ...  Acknowledgements This work was supported in part by Renesas Mobile, Texas Instruments, Xilinx, and by the US National Science Foundation under grants CNS-0551692, CNS-0619767, EECS-0925942 and CNS-0923479  ... 
doi:10.1007/s11265-011-0617-7 fatcat:plaoxwqkuvhrjbzv2s2nctoawa

A Network-on-Chip-based turbo/LDPC decoder architecture

C. Condo, M. Martina, G. Masera
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
High level modeling is exploited to drive the NoC optimization for a given set of both turbo and Low-Density-Parity-Check (LDPC) codes to be supported.  ...  of multi-standard decoders.  ...  The intrinsic differences between the turbo and LDPC decoding algorithms and their iterative nature make the design of high throughput, flexible turbo/LDPC decoder architectures a challenging task.  ... 
doi:10.1109/date.2012.6176715 dblp:conf/date/CondoMM12 fatcat:nvvy4hpeljd4vovg2bg337qdsa

Further Specialization of Clustered VLIW Processors: A MAP Decoder for Software Defined Radio

Pablo Ituero Ituero, Marisa López-Vallejo López-Vallejo
2008 ETRI Journal  
The performance-area trade-off of the proposed architecture achieves a throughput of 8 cycles per symbol with very low power dissipation.  ...  However, the complex and power consuming implementation of the maximum a posteriori (MAP) algorithm, employed by turbo decoders, sets hurdles to this goal.  ...  Each core independently decodes a set of data so that the throughput is incremented n times. Depending on the power and performance needs of the system, the number of activated cores changes.  ... 
doi:10.4218/etrij.08.0107.0076 fatcat:yelt2yyya5f7tkuat5rg6jicem
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