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Perovskite Exciton-Polaritons

Jun Zhang
2019 Journal of Semiconductors  
The ultra-low voltage design is also driven by technology scaling as well as leakage and reliability considerations.  ...  Nanjian Wu (Institute of Semiconductors, CAS, Beijing, China) doi: 10.1088/1674-4926/40/2/020204 HIGH POWER-EFFICIENT SoC CHIP A 130-nm ferroelectric nonvolatile system-on-chip for internet of things IEEE  ...  In view of distinct advantages of superior switching energy, low switching voltage, and enhanced logic density, MESO logic may enable entirely new computer architectures that may avoid the trade-offs of  ... 
doi:10.1088/1674-4926/40/2/020201 fatcat:ouihmax7wrdenkdbbtkivwdcku

Introduction to Industrial Applications of Low Power Design Methodologies

Hyung-Ock Kim, Bong-Hyun Lee, Jung-Yon Choi, Hyo-Sig Won, Kyu-Myung Choi, Hyun-Woo Kim, Seung-Chul Lee, Seung-Ho Hwang
2009 JSTS Journal of Semiconductor Technology and Science  
A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.  ...  We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias.  ...  This SoC is fabricated in 45 nm low power CMOS technology of triple well and eight metal layers for signal routing.  ... 
doi:10.5573/jsts.2009.9.4.240 fatcat:6p3ufih5sbd7vgsc6gxdfth74q

Embedding Mixed-Signal Design in Systems-on-Chip

J.M. Rabaey, F. De Bernardinis, A.M. Niknejad, B. Nikolic, A. Sangiovanni-Vincentelli
2006 Proceedings of the IEEE  
Innovative approaches and new design methodologies are needed to integrate digital, analog and RF components in CMOS systems-on-a-chip smaller than 100 nm.  ...  ABSTRACT | With semiconductor technology feature size scaling below 100 nm, mixed-signal design faces some important challenges, caused among others by reduced supply voltages, process variation, and declining  ...  Acknowledgment The authors wish to acknowledge the contributions of the students and sponsors of the Berkeley Wireless Research center, as well as the SRC and the SIA MARCO centers (GSRC and C2S2) to the  ... 
doi:10.1109/jproc.2006.873609 fatcat:bfsn4niuozbtzmyccioarvqyuq

2001 technology roadmap for semiconductors

A. Allan, D. Edenfeld, W.H. Joyner, A.B. Kahng, M. Rodgers, Y. Zorian
2002 Computer  
Acknowledgments We acknowledge the efforts of the many individuals who contributed to making the 2001 edition of The International Technology Roadmap for Semiconductors a successful endeavor.  ...  Memory content outstrips logic content faster with LSTP (low standby power) devices because they have much higher operating power than LOP (low operating power) devices.  ...  The second approach derives the power requirements bottom-up from the implied logic and memory content, as well as process and circuit para-The Roadmap specifies a mixedsignal CMOS transistor that uses  ... 
doi:10.1109/2.976918 fatcat:mv3q7f3l2zfjng2i5rvipkdhsi

Leakage current in low standby power and high performance devices

Geoffrey C-F Yeap
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In the 2001 International Technology Roadmap for Semiconductors (ITRS) [1] the driver for the high performance logic is maximizing MOSFET intrinsic speed, while the driver for low standby power logic is  ...  In this paper, trends and challenges for each leakage current component in low standby power and high performance devices are discussed from the perspective of the 2001 ITRS and recently reported literatures  ...  The author acknowledges the data from 2001 ITRS Process Integration, Device, and Structures (PIDS) Technical Working Group, and the discussions with Peter Zeitzoff and Jim Chung.  ... 
doi:10.1145/505388.505395 dblp:conf/ispd/Yeap02 fatcat:rn75e2zci5fulocmzqvbpxb7be

Ultra-Low-Power Embedded SRAM Design for Battery- Operated and Energy-Harvested IoT Applications [chapter]

Arijit Banerjee
2018 Green Electronics  
Such ULP SoC requires both logic and the embedded static random access memory (SRAM) in the processor to operate at very low supply voltages.  ...  With technology scaling for bulk and FinFET devices, logic has demonstrated to operate at low minimum operating voltages (V MIN ).  ...  SRAMs to enable technology scaling for SRAMs in 7 nm node and beyond.  ... 
doi:10.5772/intechopen.76765 fatcat:d4wsqfggmjg4zgo3xchmblcm4q

The driving force for development of IC and system in future: Reducing the power consumption and improving the ratio of performance to power consumption

YangYuan Wang
2011 Science China Information Sciences  
With the development of information technology, integrated circuits (IC) and system which target high performance and low power consumption have widely penetrated to all the aspects of national economy  ...  This paper will discuss the related research topics on Green micro/nanoelectronics, including low-power design, novel low-power devices, manufacturing processes for low power applications and related micro  ...  Cai Yimao and Prof. Zhang Xing are greatly appreciated for their many powerful help to prepare the article.  ... 
doi:10.1007/s11432-011-4229-4 fatcat:maf5on4ffffa5fct2qvat3nwpm

Low Power Design for Future Wearable and Implantable Devices

Katrine Lundager, Behzad Zeinali, Mohammad Tohidi, Jens Madsen, Farshad Moradi
2016 Journal of Low Power Electronics and Applications  
supply voltage utilizing low-voltage design techniques.  ...  Furthermore, we will describe techniques to lower the power consumption of a design including digital, analog and memory blocks.  ...  (It should be noted since the 16 nm CMOS technology is not available for us, we have compared the two analog circuits in the 14 nm FinFET and 65 nm CMOS technologies.  ... 
doi:10.3390/jlpea6040020 fatcat:tf7shjsb25ckjmobfshjrxyqmm

Power Supply Noise in SoCs: Metrics, Management, and Measurement

Karim Arabi, Resve Saleh, Xiongfei Meng
2007 IEEE Design & Test of Computers  
Using a 90-nm technology with a 2.0-nm oxide thickness and a 1.0 V power supply, we can estimate the corresponding gate leakage current density, J, as 3 3 10 27 A/mm 2 for NMOS and 239 Figure 3.  ...  However, at 90-nm and smaller technologies, SVD verification is not enough to ensure power integrity.  ...  Acknowledgments We thank the Natural Sciences and Engineering Research Council (NSERC) and PMC-Sierra for their support of this work.  ... 
doi:10.1109/mdt.2007.79 fatcat:prvja65hhrfwbiecdr3ol32w6a

Architectural and Circuit Design Techniques for Power Management of Ultra-Low-Power MCU Systems

Michael Lueders, Bjoern Eversmann, Johannes Gerber, Korbinian Huber, Ruediger Kuhn, Michael Zwerg, Doris Schmitt-Landsiedel, Ralf Brederlow
2014 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
Field Programmab le Gate Arrays (FPGAs) are widely used for imp lementation of dig ital system design due to their flexibility, low time-to-market, growing density and speed.  ...  But nowadays research extensively focuses on power too. Hence this paper demonstrates so me of the most utilized and efficient techniques for Power optimizat ion and reduction in FPGAs currently.  ...  The techniques used for static power reduction reduces power upto 60-90% and dynamic power reduction techniques reduces power upto 30-50%.  ... 
doi:10.1109/tvlsi.2013.2290083 fatcat:j2wsmzogunazpbwdx3wicplemu

Circuit Techniques for Leakage Reduction [chapter]

2018 Low-Power Electronics Design  
, A.P., Dual-threshold voltage techniques for low-power digital circuits, IEEE J. of Solid-State Circuits, 35, 1009, 2000. [17] Sirisantana, N., Wei, L., and Roy, K., High-performance low-power CMOS circuits  ...  the reduction of the supply voltage, the use of analog circuits replacing digital ones, and the design of fast and parallel circuits allowing a supply voltage reduction just satisfying to the speed constraints  ... 
doi:10.1201/9781420039559-19 fatcat:e7eeytdq2rba3d2erlvbyqtkn4

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170C

2016 IEEE Journal of Solid-State Circuits  
A spread spectrum clock generation and a clock phase shift technique are introduced for charge pump clock generation in order to suppress EMI noise due to high write throughput of code flash macros, and  ...  TASPEC is particularly useful for a data flash macro with one million rewrite cycles.  ...  circuits, embedded-flash memory for MCU, embedded non-volatile memory technology, and related technology platforms and analog IPs for MCU and SOC products.  ... 
doi:10.1109/jssc.2015.2467186 fatcat:q5nvrfxgqzasbgmarzppn47ps4

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS

B.H. Calhoun, Yu Cao, Xin Li, Ken Mai, L.T. Pileggi, R.A. Rutenbar, K.L. Shepard
2008 Proceedings of the IEEE  
We discuss new techniques for logic circuits and interconnect, for memory, and for clock and power distribution. We survey work to build accurate simulation models for nanoscale devices.  ...  Small transistors necessitate big changes, in the way digital circuits are modeled and optimized for manufacturability, and new strategies for logic, memory, clocking and power distribution.  ...  They are also grateful to their many faculty and student colleagues in C2S2 for their ideas and inputs on this paper.  ... 
doi:10.1109/jproc.2007.911072 fatcat:dxmkxqiazffjzfv24okubw4zeu

Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things

2017 Electronics  
Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed.  ...  In this review article for Internet of Things (IoT) applications, important low-power design techniques for digital and mixed-signal analog-digital converter (ADC) circuits are presented.  ...  Jin Lin contributes to low power SAR ADC and hybrid ΔƩ SAR ADC designs. Qutaiba Alasa makes a contribution in polymorphic gate logic locking using silicon nanowire and all spin logic devices.  ... 
doi:10.3390/electronics6030067 fatcat:ozssarlb2ng5pcdsupo2hljyna

Embedded DRAM: Technology platform for the Blue Gene/L chip

S. S. Iyer, J. E. Barth, P. C. Parries, J. P. Norum, J. P. Rice, L. R. Logan, D. Hoyniak
2005 IBM Journal of Research and Development  
We also discuss the evolution of embedded DRAM technology into a higherperformance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance  ...  We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM  ...  Center line in East Fishkill, New York, for building the prototypes and early user hardware.  ... 
doi:10.1147/rd.492.0333 fatcat:feb76guwfzfobghzgtjwovcxke
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