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Low-Power Soft Error Hardened Latch [chapter]

Hossein Karimiyan Alidash, Vojin G. Oklobdzija
2010 Lecture Notes in Computer Science  
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation.  ...  The proposed circuit has low power consumption with negative setup time and low timing overhead.  ...  TG1 and TG2, are conducting and works as a low-pass filter [13] . The hysteresis Fig. 3 . The Soft Error Hardened Latch effect is achieved using MP3 and MN3.  ... 
doi:10.1007/978-3-642-11802-9_30 fatcat:xvfutw6yorgjdeexpcg5mmqyoq

Low-Power Soft Error Hardened Latch

Hossein Karimiyan Alidash, Vojin G. Oklobdzija
2010 Journal of Low Power Electronics  
This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation.  ...  The proposed circuit has low power consumption with negative setup time and low timing overhead.  ...  TG1 and TG2, are conducting and works as a low-pass filter [13] . The hysteresis Fig. 3 . The Soft Error Hardened Latch effect is achieved using MP3 and MN3.  ... 
doi:10.1166/jolpe.2010.1073 fatcat:7s3mvaiufzckrmvjwruvdojlpq

Soft error filtered and hardened latch

]Hossein Karimiyan Alidash, Sayed Masoud Sayedi, Hossein Saidi, Vojin G. Oklobdzija
2009 2009 IEEE 8th International Conference on ASIC  
this paper presents a low-power soft errorhardened latch suitable for reliable circuits.  ...  The proposed circuit uses redundant feedback loop to protect latch circuit against soft error on the internal nodes and skewed CMOS to filter out transients resulting from particle hit on combinational  ...  PROPOSED SOFT ERROR HARDENED LATCH This section proposes a new soft error hardened edge triggered latch which is based on temporal redundancy, dual feedback loop and incorporates SET glitch filtering.  ... 
doi:10.1109/asicon.2009.5351360 fatcat:hharrwz2o5hhricdzmoxl2qj3m

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits

Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard
2021 Proceedings of the 2021 on Great Lakes Symposium on VLSI  
Soft error is one of the major reliability issue with technology scaling. In this work, we propose a radiation hardened voltage bootstrapped schmitt trigger (VB-ST) latch.  ...  and the lowest soft error rate ratio when compared to existing latches.  ...  error rate with lower power dissipation of the latch.  ... 
doi:10.1145/3453688.3461489 fatcat:3s2jjygeyrciramsprtaoj5vma

LIHL: Design of a Novel Loop Interlocked Hardened Latch

Hui Xu, Xuan Liu, Guo Yu, Huaguo Liang, Zhengfeng Huang
2021 Electronics  
This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL).  ...  Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay.  ...  The LIHL PDP is reasonably low, indicating that the design can tolerate soft errors while maintaining low power consumption and propagation delay. Figure 17 . 17 Figure 17.  ... 
doi:10.3390/electronics10172090 fatcat:vzitw6jh6ramzn6xwsltc7zc2u

A power-delay-product efficient and SEU-tolerant latch design

Pei Liu, Tian Zhao, Feng Liang, Jizhong Zhao, Peilin Jiang
2017 IEICE Electronics Express  
In this paper, we propose a SEU-tolerant latch with low power-delay-product (PDP) that combines a SEU-tolerant cross-coupled structure with isolation operation of flipped state.  ...  The simulation results with 180 nm and 40 nm CMOS technology show that the proposed latch can achieve outstanding SEU-tolerance (Q critical > 10 fC) and a relatively low PDP of 0.0095 fs×J for 40 nm CMOS  ...  Lin, et al.: "Soft-error hardening designs of nanoscale CMOS latches," IEEE VLSI Test Symposium (2009) 41 (DOI: 10.1109/VTS.2009.10). [16] S. M.  ... 
doi:10.1587/elex.14.20170972 fatcat:4ygztxrihjg2pbzpdt3gaabnde

High-Performance Double-Node-Upset-Tolerant and Triple-Node-Upset-Tolerant Latch Designs

Hui Xu, Le Zhou, Huaguo Liang, Zhengfeng Huang, Cong Sun, Yafei Ning
2021 Electronics  
To avoid soft errors in integrated circuits, this paper presents two high-performance latch designs, namely LOCDNUTRL and LOCTNUTRL, protecting against double-node upset (DNU) and triple-node upset (TNU  ...  average compared with the state-of-the-art hardened latches.  ...  What is more serious is that when some latches tolerate soft errors, the output generates an HIS.  ... 
doi:10.3390/electronics10202515 fatcat:ibrez77bnbeyncvuyeinhtfusi

Evaluation and Test of Production Defects in Hardened Latches

Ruijun MA, Stefan HOLST, Xiaoqing WEN, Aibin YAN, Hui XU
2022 IEICE transactions on information and systems  
As modern CMOS circuits fabricated with advanced technology nodes are becoming more and more susceptible to soft-errors, many hardened latches have been proposed for reliable LSI designs.  ...  As the first comprehensive study bridging the gap between hardened latch design and LSI testing, the findings of this paper will significantly improve the soft-error-related reliability of LSI designs  ...  Problem-2 (Low Soft-Error Tolerability): If a defect exists in a hardened latch due to imperfect production, the hardened latch's soft-error tolerability may be reduced, Copyright c 2022 The Institute  ... 
doi:10.1587/transinf.2021edp7216 fatcat:znr32ebvofaqtbu7obxzarojyi

A highly reliable SEU hardened latch and high performance SEU hardened flip-flop

Riadul Islam
2012 Thirteenth International Symposium on Quality Electronic Design (ISQED)  
The proposed latch exhibits as much as 17% lower power-delay product (PDP) compared to recently reported SEU hardened latch, and the proposed flip-flop exhibits lower or comparable PDP compared to recently  ...  We have investigated power con sumption s, pr opagation delay, SET sen sitivity an d the area penalty of the proposed latch and flip-flop comparing with the recently reported SEU hardened latches and flip-flops  ...  Soft error robust latch Nicolaidis et. al. proposed a highly robust hardened latch uses blocking feedback transistors to mitigate SEUs [7] .  ... 
doi:10.1109/isqed.2012.6187516 dblp:conf/isqed/Islam12 fatcat:ooqkmxnk6ffqjfgqrxka5f3ski

Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Ehab A. Hamed, Inhee Lee
2021 Electronics  
Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay.  ...  In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs).  ...  The master latch of TGFF can be easily upset by the soft errors that happen when the CLK is high (in the hold state of the master latch) while the slave latch can be upset when the CLK is low (in the hold  ... 
doi:10.3390/electronics10131572 fatcat:kb6s64porrfajiq645ldloz4ly

A Novel Radiation Hardened Parallel IO Port for Highly Reliable Digital IC Design

Nastaran Rajaei, Ramin Rajaei
2016 International Journal of Modern Education and Computer Science  
This article proposes a radiation hardened parallel IO port capable of tolerating radiation induced soft errors including single event upsets (SEUs) as well as single event transients (SETs).  ...  To investigate the soft error tolerance capability of the proposed design, we simulated it using the Cadence tool and showed its offered advantages.  ...  SET soft errors.  ... 
doi:10.5815/ijmecs.2016.09.03 fatcat:ugh5ayulxzamtd6diggw3dceba

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Aibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui, Zuobin Ying, Patrick Girard, Xiaoqing Wen
2020 2020 57th ACM/IEEE Design Automation Conference (DAC)  
TNU hardened latch (TNUHL) that cannot filter SETs.  ...  with low-cost.  ...  Area Comparison It can be seen from Fig. 5-(b) that the unhardened latch has the smallest area, since soft-error-hardened latches have to use extra transistors.  ... 
doi:10.1109/dac18072.2020.9218704 dblp:conf/dac/YanFZZ0Y0W20 fatcat:gqars7kbojgpzj4bs34lsflvzi

A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Duckhoon Ro, Changhong Min, Myounggon Kang, Ik Joon Chang, Hyung-Min Lee
2019 Sensors  
However, radiation environments, such as space, flight, nuclear power plants, and nuclear fusion reactors, as well as high-reliability applications, such as automotive semiconductor systems, suffer from  ...  Also, the proposed radiation-hardened SAR ADC with delay-based dual feedback flip-flops was designed and verified by utilizing compact transistor models, which reflect radiation effects to CMOS parameters  ...  The timing diagram in Figure 6b clearly shows why the proposed radiation-hardened latch structure is robust to soft errors.  ... 
doi:10.3390/s20010171 pmid:31892184 pmcid:PMC6983195 fatcat:cxc6jkgwj5cyjmzxgx4ajh5y3y

Dual-Modular-Redundancy and Dual-Level Error-Interception based Triple-Node-Upset Tolerant Latch Designs for Safety-Critical Applications

Aibin Yan, Zhihui He, Jun Zhou, Jie Cui, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard
2021 Microelectronics Journal  
This paper further presents a low-cost version of the DDETT latch, namely LCDDETT.  ...  Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and  ...  The latch has the same soft error tolerance compared to the DDETT latch and can achieve very low overhead in terms of power dissipation, silicon area and DPAP.  ... 
doi:10.1016/j.mejo.2021.105034 fatcat:o5hxs7ubmbb4ll7ayuwlwsqxte

On the radiation-induced soft error performance of hardened sequential elements in advanced bulk CMOS technologies

N. Seifert, V. Ambrose, B. Gill, Q. Shi, R. Allmon, C. Recchia, S. Mukherjee, N. Nassif, J. Krause, J. Pickholtz, A. Balasubramanian
2010 2010 IEEE International Reliability Physics Symposium  
This work summarizes the measured soft error rate benefits and design tradeoffs involved in the implemented hardening techniques.  ...  The radiation robustness of two types of circuit-level soft error mitigation techniques has been tested: 1) SEUT (Single Event Upset Tolerant), an interlocked, redundant state technique, and 2) a novel  ...  The soft error rate under charge sharing conditions SER CS then equals the integral over the product of the SBU soft error rate SER(Qcrit p (Qs(x)) at the primary node p with P(Qs(x)|Qcrit(Qs(x))) [21  ... 
doi:10.1109/irps.2010.5488831 fatcat:uejz25xbwrfrlgrk2t3kdpkofq
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