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Low-Power High-Throughput LDPC Decoder Using Non-Refresh Embedded DRAM

Youn Sung Park, David Blaauw, Dennis Sylvester, Zhengya Zhang
2014 IEEE Journal of Solid-State Circuits  
Index Terms-Embedded DRAM, LDPC code, LDPC decoder architecture, low-power DSP design. 0018-9200  ...  We integrate 32 5x210 non-refresh eDRAM arrays in a row-parallel LDPC decoder suitable for the IEEE 802.11ad standard.  ...  Urard for suggestions on the LDPC decoder design.  ... 
doi:10.1109/jssc.2014.2300417 fatcat:4vklf6okezeudnmobmjdugeqye

Errors in Flash-Memory-Based Solid-State Drives: Analysis, Mitigation, and Recovery [article]

Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo, Onur Mutlu
2018 arXiv   pre-print
the experimental characterization, we describe several mitigation and recovery techniques, including (1) cell-tocell interference mitigation; (2) optimal multi-level cell sensing; (3) error correction using  ...  We expect that as the capacity of each DRAM chip increases, (a) the refresh latency, (b) the DRAM throughput lost during refresh operations, and (c) the power consumed by refresh will all increase.  ...  The additional time spent on refresh causes the DRAM data throughput loss due to refresh to become more severe in denser DRAM chips, as shown in Figure 45b .  ... 
arXiv:1711.11427v2 fatcat:rvnbeg4eevfa7lczf2h2ificxi

Architectural Techniques for Improving NAND Flash Memory Reliability [article]

Yixin Luo
2018 arXiv   pre-print
flash reliability at a low cost.  ...  We analyze flash error characteristics and workload behavior through experimental characterization, and design new flash controller algorithms that use the insights gained from our analysis to improve  ...  As prior work observes from We expect that as the capacity of each DRAM chip increases, (a) the refresh latency, (b) the DRAM throughput lost during refresh operations, and (c) the power consumed by refresh  ... 
arXiv:1808.04016v1 fatcat:fotned4yajc2xmaoezwjdrgypu

2020 Index IEEE Transactions on Circuits and Systems II: Express Briefs Vol. 67

2020 IEEE Transactions on Circuits and Systems - II - Express Briefs  
., Design of a Single Chip PWM Driver Circuit for Inverter Welding Power Source; TCSII April 2020 720-724 Jacobsson, S., see Castaneda, O., TCSII May 2020 891-895 Jafari, E., and Binazadeh, T., Robust  ...  S., TCSII Feb. 2020 250-254 Jalali, M., see Kari Dolatabadi, A., TCSII Oct. 2020 1740-1744 Jalili, M., see Fang, X., TCSII March 2020 511-515 Jana, B., Roy, A.S., Saha, G., and Banerjee, S., A Low-Error  ...  Lunglmayr, M., +, TCSII Dec. 2020 3507-3511 One-Shot Refresh: A Low-Power Low-Congestion Approach for Dynamic Memories.  ... 
doi:10.1109/tcsii.2020.3047305 fatcat:ifjzekeyczfrbp5b7wrzandm7e

2020 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 67

2020 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
., +, TCSI May 2020 1729-1739 Iterative decoding Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Con- flicts Resolution and Efficient Hardware Utilization.  ...  ., +, TCSI Jan. 2020 322-335 Flexible High Throughput QC-LDPC Decoder With Perfect Pipeline Conflicts Resolution and Efficient Hardware Utilization.  ...  Serna, J.A.d.l .O., TCSI Dec. 2020 5092-5100 High-Efficiency Low Voltage Inverse Class-F Power Amplifier Design Based on Harmonic Control Network Analysis.  ... 
doi:10.1109/tcsi.2021.3055003 fatcat:kbmst5td2bbvtl7vpbj3knnkri

Simultaneous Wireless Information and Power Transfer (SWIPT): Recent Advances and Future Challenges

Tharindu D. Ponnimbaduge Perera, Dushantha Nalin K. Jayakody, Shree Krishna Sharma, Symeon Chatzinotas, Jun Li
2018 IEEE Communications Surveys and Tutorials  
, use of high frequency in supply and the infeasibility of air ionization techniques [9] .  ...  2 electricity and putting it to work based on power requirements. The ambient environment contains high-quality energy sources compared to currently available batteries and charged supercapacitors.  ...  LDPC decoder using non-refresh embedded DRAM has been designed in [185] .  ... 
doi:10.1109/comst.2017.2783901 fatcat:iw2mg5se4bhzpcqgcdd5dfgaoi

Control and Visualisation of a Software Defined Radio System on the Xilinx RFSoC Platform Using the PYNQ Framework

Joshua Goldsmith, Craig Ramsay, David Northcote, Kenneth W. Barlee, Louise H. Crockett, Robert W. Stewart
2020 IEEE Access  
In doing so, we highlight features that can be extremely useful for prototyping radio system design.  ...  They also thank Xilinx for the use of a ZCU111 RFSoC development board, and software donations.  ...  They also extend their appreciation to two of our research colleagues at Strathclyde, Andrew Maclellan, and Marius Šiaučiulis, who have provided useful feedback during the production of this paper.  ... 
doi:10.1109/access.2020.3008954 fatcat:523zk3j6fva5bbb2rwmcawqnea

Novel Approaches Toward Area- and Energy-Efficient Embedded Memories

Pascal Andreas Meinerzhagen
2014
I would also like to thank Robert Giterman who helped us tremendously with the measurement of various gain-cell eDRAM test chips and who continued research into low-power gain-cell memories.  ...  Kulkarni, who dedicated an amazing amount of his time to me (up to three 1:1 meetings per week), and from whom I learned tons in the field of analog and digital IC design, particularly in the field of power  ...  Standard-Cell Based Memories (SCMs) for High-Performance VLSI Systems Application Example: Low-Power LDPC Decoder This Section investigates the use of the best-practice SCM in a low-power LDPC decoder  ... 
doi:10.5075/epfl-thesis-6074 fatcat:4q3q7qy6p5f7nakakhkwyqmi2y

Phase change memory technology

Geoffrey W. Burr, Matthew J. Breitwisch, Michele Franceschini, Davide Garetto, Kailash Gopalakrishnan, Bryan Jackson, Bülent Kurdi, Chung Lam, Luis A. Lastras, Alvaro Padilla, Bipin Rajendran, Simone Raoux (+1 others)
2010 Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics  
), the role of coding, and possible routes to an ultra-high density PCM technology.  ...  We survey the current state of phase change memory (PCM), a non-volatile solid-state memory technology built around the large electrical contrast between the highly-resistive amorphous and highly-conductive  ...  Check (LDPC) codes with iterative decoding methods [242] .  ... 
doi:10.1116/1.3301579 fatcat:axaan4wdbbhf3a6ii4wrppriba

D3.1 Communication of IoT Devices

Efstathios Katranaras, Guillaume Vivier, Ignacio Garcia Zuazola, Jaime Ruiz Alonso, Ignacio Benito Frontelo, Ahmad Nimr, Roberto Bomfin, Ivo Bizon Franco de Almeida, Albert Marín-Bernad, David Gomez-Barquero, Cristina Avellan, José Luis Cárcel Cerver (+8 others)
2021 Zenodo  
has the objective of capturing the state of the art (SoA) technologies, from the device standpoint, supporting IoT and the planned innovations of iNGENIOUS in this regard, which are also mapped to the use  ...  For instance, the Low Power Wide Area (LPWA) applications are characterised by targeting long range, low-power and low-cost use cases with relaxed throughput requirements.  ...  ensure high throughput and low latency connectivity with the cockpit, while MR and haptic solutions will provide an immersive experience to the worker.  ... 
doi:10.5281/zenodo.4890976 fatcat:cqxyf76dtvgbhl4rh774pwubnq

RBER-Aware Lifetime Prediction Scheme for 3D-TLC NAND Flash Memory

Ruixiang Ma, Fei Wu, Meng Zhang, Zhonghai Lu, Jiguang Wan, Changsheng Xie
2019 IEEE Access  
The first problem is that the error correcting code (ECC) is often over-provisioned, as it has to be designed to tolerate the worst case to ensure data integrity, which causes longer decoding latency.  ...  values obtained in the real NAND flash-based test platform, and the experimental results show that the support vector machine (SVM) models based on our proposed lifetime prediction scheme can achieve as high  ...  INTRODUCTION NAND flash has been widely used for data storage due to its high density, high throughput, and low power.  ... 
doi:10.1109/access.2019.2909567 fatcat:x5hbzdj37vdcdgfvp6y5p3hzae

GPU accelerated onboard data processing for downlink optimisation

Rebecca Davidson
2019
low power NVIDIA Jetson TX1 GPU platform.  ...  In addition, the research documented in this thesis aims to demonstrate the viability and evaluate the advantages of using low-power GPUs in an onboard data processing system.  ...  Throughput (Gb/s) Number of Tiles  ... 
doi:10.15126/thesis.00852470 fatcat:napelwugefei7pmh3txxtg4rr4

Proceedings of the 2nd International Conference on Applied Innovations in IT [article]

Eduard Siemens, Et Al., Universitäts- Und Landesbibliothek Sachsen-Anhalt, Martin-Luther Universität, Eduard Siemens
2018
During low power modes, the master oscillator is disabled.  ...  Low-Power Single Carrier uses this encoding mainly because of the minimized power consumption, but still at the expense of less robust error correction.  ...  Electronic educational resources were developed using an educational process for training students with the specializations "Electrical Power Supply," "Automation of Technological Processes and Production  ... 
doi:10.25673/5634 fatcat:2ewwbyoilfbgrgdjbncqz6cqca

Dagstuhl Reports, Volume 6, Issue 8, August 2016, Complete Issue [article]

2017
Cryptographic designs must scale towards high-performance, high-throughput implementations while it must also accommodate small-footprint, low-latency designs.  ...  Traditional applications using pub/sub systems require large-scale deployment and high event throughput.  ...  Viral diversity is estimated to be very high and viruses are important players in many environments (e.g. unknown viruses might be causing diseases in human).  ... 
doi:10.4230/dagrep.6.8 fatcat:jhbruchpmvdthoe45w75w35wpe