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Design of a Strong-Arm Dynamic-Latch based comparator with high speed, low power and low offset for SAR-ADC [article]

Sounak Dutta
2022 arXiv   pre-print
This study provides a revised design for a dynamic-latch-based comparator that achieves the lowest latency, maximum area-efficient realisation, reduced power dissipation, and low offset.  ...  Compared to the original design, the PDP was easily reduced by approximately by 6% with offset voltage reduced by 8 mV without speed trade-off.  ...  These days, dynamic comparators are widely being used because of their low-power consumption.  ... 
arXiv:2209.07259v1 fatcat:elhotcw7wnffxjjgqtw75rrf6u

A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling

L.Y. Nathawad, R. Urata, B.A. Wooley, D.A.B. Miller
2003 IEEE Journal of Solid-State Circuits  
Dynamic offset averaging is employed to improve converter linearity.  ...  Index Terms-Analog-to-digital (A/D) conversion, CMOS analog integrated circuits, flash converter, low-temperature-grown GaAs, metal-semiconductor-metal (MSM) devices, offset averaging, optical data processing  ...  time, without averaging and with Fig. 11 . 11 First-stage low-offset latch with NMOS clamp.  ... 
doi:10.1109/jssc.2003.819172 fatcat:oywhevqxjzgyxnfolbaevwo4jy

A 1.3-Gsample/s interpolation with flash CMOS ADC based on active interpolation technique

S. Seemi, Mohd. S. Sulaiman, A. S. Farooqui
2006 Analog Integrated Circuits and Signal Processing  
The use of summing differential amplifiers operating in continuous time for interpolation and resistor averaging circuit have significantly improved the circuit's linearity.  ...  The new interpolation technique has improved the pertinent phase delay problem of voltage interpolation enormously.  ...  Offset averaging Averaging is the most common technique used to reduce offset errors [1, 5, 8, 11] . This technique has been used to improve static errors induced due to amplifiers' offset error.  ... 
doi:10.1007/s10470-006-5369-0 fatcat:jzwpvea2g5g7doc6q7dxvgvulq

A 6-bit 2 GS/s ADC in 65 nm CMOS

HaoNan Wang, Tao Wang, YuFeng Yao, Hui Wang, YuHua Cheng
2014 Science China Information Sciences  
A 6-bit 2 GS/s ADC was implemented using a 65 nm digital CMOS technology. The design is based on a single-channel flash ADC architecture, and utilizes interpolating and averaging techniques.  ...  A two-stage CML-CMOS high-speed hybrid comparator is designed for optimal speed and power performance. The total power consumption of the converter is 52 mW and the area is 0.24 mm 2 .  ...  However, it would result in high-power consumption because of extra bias current. Comparators with CMOS clocked-latch are also used to latch small swing signal into full rail-to-rail swing directly.  ... 
doi:10.1007/s11432-014-5101-0 fatcat:lhoivp247raf7jgokkudtbwgpi

Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-Based Input Voltage Range Detection Circuit
비교기 기반 입력 전압범위 감지 회로를 이용한 6비트 500MS/s CMOS A/D 변환기 설계

Shi Dai, Sang Min Lee, Kwang Sub Yoon
2013 The Journal of Korean Institute of Communications and Information Sciences  
ABSTRACT A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described.  ...  The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off.  ...  a very low input capacitance.  ... 
doi:10.7840/kics.2013.38a.4.303 fatcat:o2qlggxgazbz7jpss4a46eaonu

A 6b 1.2 GS/s 47.8 mW 0.17 mm265 nm CMOS ADC for High-Rate WPAN Systems

Hye-Lim Park, Yi-Gi Kwon, Min-Ho Choi, Young-Lok Kim, Seung-Hoon Lee, Young-Deuk Jeon, Jong-Kee Kwon
2011 JSTS Journal of Semiconductor Technology and Science  
The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 V p-p at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer  ...  with low distortion.  ...  Comparators are designed with a minimum size to reduce the overall ADC power consumption while the increased offsets are calibrated by digital techniques.  ... 
doi:10.5573/jsts.2011.11.2.095 fatcat:hruttmf7g5dmtkn7ejgn5o3hcu

High Precision SAR ADC Using CNTFET for Internet of Things

V. Gowrishankar, K.Venkatachalam
2019 Computers Materials & Continua  
These techniques are used to increase the sampling rate and precision while ensuring the linearity, power consumption and noise level are within the limit.  ...  The key components in CNTFET SAR ADCs are binary scaled charge redistribution digital to analog converter using MOS capacitors, CNTFET based dynamic latch comparator and simple SAR digital code error correction  ...  High performances and low offset voltage CNFET based two stages dynamic comparator The analog comparators are used to convert the sampled analog sensor value to a quantized single bit.  ... 
doi:10.32604/cmc.2019.07749 fatcat:a3aya36kdffh3hqbs5t4kmyxq4

An Unbalanced Clock Based Dynamic Comparator: A High-Speed Low-Offset Design Approach for ADC Applications

Vikrant Varshney, Rajendra Kumar Nagaria
2019 Advances in Electrical and Electronic Engineering  
Keywords Dynamic comparator, high speed, latch comparator, low offset design, unbalanced clock.  ...  Currently, dynamic comparator approach necessitates in high-speed and power efficient analogto-digital converter applications due to its high latching speed and ultra-low power consumption.  ...  A challenge towards high speed low power comparator is increase of kickback noise [10] and offset caused by mismatches due to threshold voltage, capacitances, and current factors.  ... 
doi:10.15598/aeee.v17i4.3326 fatcat:fgigqnhearexvmvt4jrdqkuffa

Improved StrongARM latch comparator: Design, analysis and performance evaluation

Abdullah Almansouri, Abdullah Alturki, Abdullah Alshehri, Talal Al-Attar, Hossein Fariborzi
2017 2017 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)  
This paper presents an improved StrongARM latch comparator, designed and simulated in 90nm and 32nm CMOS technologies.  ...  The proposed design provides an improvement of 7% in energy efficiency, 14% in speed and an average reduction of 41% in the clock feedthrough, compared to the conventional design.  ...  Since no offset cancellation techniques are used, the differential voltage is set to 60mV.  ... 
doi:10.1109/prime.2017.7974114 fatcat:3qd7nhgs2fg27ehnwvk65uzcpu

Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 µm CMOS Process

Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Alauddin Mohammad Ali, Mohammad Marufuzzaman, Sefer Bora Lisesivdin
2014 PLoS ONE  
The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution.  ...  Citation: Rahman LF, Reaz MBI, Yin CC, Ali MAM, Marufuzzaman M (2014) Design of High Speed and Low Offset Dynamic Latch Comparator in 0.18 mm CMOS Process. PLoS ONE 9(10): e108634.  ...  Conclusions A novel high-speed, low power and low offset dynamic latchtype comparator method is presented in this research works.  ... 
doi:10.1371/journal.pone.0108634 pmid:25299266 pmcid:PMC4191981 fatcat:z2p7jbocbfgv5axrlm4pesv7ai

A Low-Power High-Speed Dynamic Comparator with a Transconductance-Enhanced Latching Stage

Yao Wang, Mengmeng Yao, Benqing Guo, Zhaolei Wu, Wenbing Fan, Juin Jei Liou
2019 IEEE Access  
In this paper, a novel low-power, high-speed dynamic comparator with a new latching stage is presented.  ...  INDEX TERMS Dynamic comparator, high-speed, low-power, two-stage comparator.  ...  Several design techniques for lowvoltage, low-power dynamic comparators have been reported, including the charge-steering technique [9] , techniques using body-driven transistors [10] , and supply boosting  ... 
doi:10.1109/access.2019.2927514 fatcat:iu62bvka4ffwxnpoajycwnboxq

22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers

Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa
2014 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)  
A folding architecture is a well-known technique to reduce the number of comparators in an ADC while maintaining high sampling rate and low latency [1, 2] .  ...  In contrast, a folding ADC with only dynamic power consumption and without using amplifiers was reported [3] .  ...  Acknowledgments: This work was partially supported by MIC, Berkeley Design Automation for the use of the Analog Fast SPICE(AFS) Platform, and VDEC in collaboration with Cadence Design Systems, Inc.  ... 
doi:10.1109/isscc.2014.6757482 dblp:conf/isscc/MiyaharaMNOM14 fatcat:md3ues6p4fa5tavukwvnhdpodm

An offset cancellation technique for comparators using body-voltage trimming

Samaneh Babayan Mashhadi, Seyed Hadi Nasrollaholosseini, Hassan Sepehrian, Reza Lotfi
2011 2011 IEEE 9th International New Circuits and systems conference  
The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output.  ...  Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28mV to 750μV operating at 1-GHz with only 25μW power in offset cancellation  ...  The ADCs often require the comparators to be low-power, low-offset, high speed with small area.  ... 
doi:10.1109/newcas.2011.5981308 fatcat:wjbeeqhytnchtgtzwe4zk2mz3m

An offset cancellation technique for comparators using body-voltage trimming

Samaneh Babayan-Mashhadi, Reza Lotfi
2012 Analog Integrated Circuits and Signal Processing  
The proposed offset cancellation is achieved by body voltage adjustment using low-power simple analog control feedback circuit without any additional capacitive loading at the comparator output.  ...  Simulation results show that using the proposed technique the standard deviation of the comparator offset is significantly reduced from 28mV to 750μV operating at 1-GHz with only 25μW power in offset cancellation  ...  The ADCs often require the comparators to be low-power, low-offset, high speed with small area.  ... 
doi:10.1007/s10470-012-9925-5 fatcat:spwwzyih5je65c6pie654roqya

An early shutdown circuit for power reduction in high-precision dynamic comparators

N. Shahpari, M. Habibi, P. Malcovati
2020 AEU - International Journal of Electronics and Communications  
With the proposed method power consumption can be reduced in low power high precision dynamic comparators.  ...  Furthermore, a time domain offset cancellation technique is incorporated to reduce offset effects.  ...  The offset cancellation technique uses the body voltages of the input devices to compensate the offset so that it does not affect the delay of the main comparator.  ... 
doi:10.1016/j.aeue.2020.153144 fatcat:yj5m23lv6rf6diplclb3k5il3m
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