A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2015; you can also visit the original URL.
The file type is application/pdf.
Filters
A SAR-Assisted Two-Stage Pipeline ADC
2011
IEEE Journal of Solid-State Circuits
Preserved Fulltext
We propose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC. ...
The ADC achieves low-power, high-resolution and high-speed operation without calibration. The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 0.16 mm 2 . ...
The architecture achieves a calibration-free, highresolution, moderate-speed, area-efficient and power-efficient ADC design, which is difficult to achieve with traditional ADC architectures such as SAR ...
doi:10.1109/jssc.2011.2108133
fatcat:4fzhgg7gonaxxmfrcwioriholu
A 35 fJ 10b 160 MS/s pipelined-SAR ADC with decoupled flip-around MDAC and self-embedded offset cancellation
2011
IEEE Asian Solid-State Circuits Conference 2011
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
A Time-Interleaved (TI) pipelined-SAR ADC with on-chip offset cancellation technique is presented. ...
The design reuses the SAR ADC to perform offset cancellation, which significantly saves calibration area, power and time. ...
The prototype ADC draws only 2.72mW power from the 1.1-V supply and has a FoM of 35fJ/conv.-step.
ACKNOWLEDGMENT The authors would like to thank Hou-Lon Choi (Justin) for the measurement support. ...
doi:10.1109/asscc.2011.6123604
dblp:conf/asscc/0001CSUMM11
fatcat:aymaq55x3jdfna2m4grnyefggu
A Survey on Analog-to-Digital Converter Integrated Circuits for Miniaturized High Resolution Ultrasonic Imaging System
2022
Micromachines
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
In this paper, the architecture and performance of ADC for UIS, including successive approximation register (SAR) ADC, sigma-delta (Σ-∆) ADC, pipelined ADC, and hybrid ADC, have been systematically introduced ...
As traditional ultrasonic imaging systems (UIS) are expensive, bulky, and power-consuming, miniaturized and portable UIS have been developed and widely utilized in the biomedical field. ...
[64] proposed a low-power pipelined-SAR ADC, which adopts the booster barrel brigade device (BBD) to deal with the residual charge, as shown in Figure 16b . ...
doi:10.3390/mi13010114
pmid:35056279
pmcid:PMC8779678
fatcat:nxirhfhgzjcvlojql2k6sflxfi
A Calibration-Free, 16-Channel, 50-MS/s, 14-Bit, Pipelined-SAR ADC with Reference/Op-Amp Sharing and Optimized Stage Resolution Distribution
2022
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
Based on this, a three-stage, pipelined-SAR ADC architecture with reference/op-amp sharing and optimized stage resolution distribution is proposed. ...
This paper presents a calibration-free, 16-channel, 14-bit, 50-MS/s, pipelined successive approximation register (pipelined-SAR) analog-to-digital converter (ADC) for ultrasound imaging systems. ...
Pipelined-SAR ADC Figure 2 illustrates the architecture of a pipelined-SAR ADC. ...
doi:10.3390/electronics11050749
fatcat:n3zsb3cd7neqzfamjs56i72bwi
A 1 GS/s 12-Bit Pipelined/SAR Hybrid ADC in 40 nm CMOS Technology
2020
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2020; you can also visit the original URL.
The file type is application/pdf.
A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two ...
The core ADC consumes 94 mW, occupies an active area of 0.47 mm × 0.25 mm. The Walden figure of merit reaches 0.14 pJ/step with a Nyquist input. ...
Proposed ADC Architecture The block diagram of the proposed pipelined/SAR hybrid ADC is presented in Figure 1a . ...
doi:10.3390/electronics9020375
fatcat:27yugmsyazbpbjhic2ewaqhcdy
9-bit time–digital-converter-assisted compressive-sensing analogue–digital-converter with 4 GS/s equivalent speed
2016
Electronics Letters
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2019; you can also visit the original URL.
The file type is application/pdf.
With a voltage-time-converter serving as the cross-domain residue conveyer, the proposed twostage self-timed pipeline ADC architecture hybrids a voltage-domain comparator-interleaved successive-approximation ...
(SAR) ADC frontend and a time-domain locally readjusted folding two-dimensional Vernier TDC back-end. ...
As shown in Fig. 1b , the two-stage self-timed pipeline architecture hybrids a voltage-domain 5-bit comparator-interleaved SAR-ADC and a time-domain 5-bit locally readjusted folding two-dimensional (2D ...
doi:10.1049/el.2015.3778
fatcat:bquklpflyfgk5mqrjuitxfq7tm
A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS
2021
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2022; you can also visit the original URL.
The file type is application/pdf.
A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. ...
A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. ...
Acknowledgments: The authors would like to thank Shuai Li from State Key Laboratory of ASIC & System, Fudan University for ADC measurement supporting. ...
doi:10.3390/electronics10243173
fatcat:hfler3brara67li4yakpmc7qhu
A 12-bit 110MS/s 4-stage single-opamp pipelined SAR ADC with ratio-based GEC technique
2012
2012 Proceedings of the ESSCIRC (ESSCIRC)
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
This paper presents a 12-bit 110MS/s 4-stage pipelined SAR ADC integrated through a single low-gain op-amp. ...
The ADC obtains an average SNDR of 63 dB and SFDR of 75.2 dB at 110MS/s consuming analog power of 11.5mW from a 1.2-V supply. ...
INTRODUCTION With its intrinsic lower power consumption, pipelined SAR ADC [1] [2] has already become a popular alternative topology for traditional pipeline ADC. ...
doi:10.1109/esscirc.2012.6341336
dblp:conf/esscirc/WangCSUWM12
fatcat:riftycib3jewrmhg46dcm45qqe
Design of 16-Bit SAR ADC Using DTMOS Technique
2021
Turkish Journal of Computer and Mathematics Education
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. ...
It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. ...
In this thesis, it is highly concentrated on low power consumption with minimized supply voltages with low power optimized techniques. ...
doi:10.17762/turcomat.v12i3.1339
fatcat:y6a2am4k3bdctdnk5b43m3troa
Design of 16-Bit SAR ADC Using DTMOS Technique
2021
Turkish Journal of Computer and Mathematics Education
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. ...
It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. ...
In this thesis, it is highly concentrated on low power consumption with minimized supply voltages with low power optimized techniques. ...
doi:10.17762/turcomat.v12i5.806
fatcat:cudez44cefb5vmdsbvdju2azgu
VLSI Design of Low Power High Speed 4 Bit Resolution Pipeline ADC In Submicron CMOS Technology
2011
International Journal of VLSI Design & Communication Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The paper presents a design of 4 bit Pipeline ADC with low power dissipation implemented in <0.18µm. ...
specially power consumption . ...
Pipeline ADC versus Other ADCs Power dissipation of Pipeline ADCs varies with the sampling rate unlike Flash and SAR architectures. Hence find applications in PDAs. ...
doi:10.5121/vlsic.2011.2408
fatcat:mjkdlvwy3retdlggoh3dgriqju
A 7 bit 1 GS/s pipelined folding and interpolating ADC with coarse-stage-free joint encoding
2014
IEICE Electronics Express
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2018; you can also visit the original URL.
The file type is application/pdf.
The power consumption is 98 mW with sampling rate of 1.0 GS/s and supply voltage of 1.2/ 2.5 V. The peak figure-of-merit (FoM) is 1.54 pJ/conversion-step. ...
An improved joint encoding method is proposed to eliminate the coarse sub-ADC and reduce the power consumption. ...
The second is the sub-ranging architecture [4] . The third is the architecture proposed in this paper. In the first one, SAR ADC has a simple architecture and a less power consumption. ...
doi:10.1587/elex.11.20140371
fatcat:y6nggjlvdfh3rhnijzvt6oqbnq
A 40-mW 7-bit 2.2-GS/s Time-Interleaved Subranging CMOS ADC for Low-Power Gigabit Wireless Communications
2012
IEEE Journal of Solid-State Circuits
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
A 7-bit, 2.2-GS/s time-interleaved subranging CMOS analog-to-digital converter (ADC) for low-power gigabit wireless communication system-on-a-chip (SoC) is presented. ...
A time-splitting subranging architecture is invented to significantly boost the speed of individual ADC channels. ...
Recent publications have adopted successive-approximationregister ADCs (SAR-ADCs) [3] , [7] and pipelined ADCs [4] as the sub-ADCs in a time-interleaved architecture. ...
doi:10.1109/jssc.2012.2196731
fatcat:f5wr5zblgfb5ndnxtlrfosr76m
A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier
2021
Electronics
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2021; you can also visit the original URL.
The file type is application/pdf.
By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented ...
In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design ...
Architecture
2.1. Pipelined Noise-Shaping SAR ADC ...
doi:10.3390/electronics10161968
fatcat:2mu2hpql65fflej45kpgyqvp3m
Adaptive Resolution ADC Array for an Implantable Neural Sensor
2011
IEEE Transactions on Biomedical Circuits and Systems
Preserved Fulltext
A copy of this work was available on the public web and has been preserved in the Wayback Machine. The capture dates from 2017; you can also visit the original URL.
The file type is application/pdf.
The base ADC has been implemented in 0.13 m CMOS as a 100 kS/s SAR ADC whose resolution can be varied from 3 to 8 bits with corresponding power consumption of 0.23 W to 0.90 W achieving an ENOB of 7.8 ...
Index Terms-Adaptive signal acquisition, analog-digital conversion, neural prosthesis, ultra low power. ...
Fig. 9 shows that the CR-SAR architecture is more power efficient than pipeline or flash ADC architectures over a wide range of resolutions. ...
doi:10.1109/tbcas.2011.2145418
pmid:23851200
fatcat:3ixlvqnlpffpvbmfgpzlqu4mj4
« Previous
Showing results 1 — 15 out of 279 results