Filters








403 Hits in 2.7 sec

Low Transition LFSR for BIST-Based Applications

M. Tehranipoor, M. Nourani, N. Ahmed
2005 14th Asian Test Symposium (ATS'05)  
LT-LFSR is independent of circuit under test and flexible to be used for both BIST and scan-based BIST architectures.  ...  This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within random test pattern and between  ...  A low power BIST based on state correlation analysis proposed in [6] .  ... 
doi:10.1109/ats.2005.77 dblp:conf/ats/TehranipoorNA05 fatcat:bfrwccgejvactkks65socxaauu

Design of Low Transition Pseudo-Random Pattern Generator for BIST Applications

Lubna Naim, Tarana A. Chandel
2014 International Journal of Computer Applications  
This new technique represent low transition pattern pseudorandom generator (LT-PRG) for Test-per-Clock and Test-per-Scan BIST applications.  ...  This paper presents a modification in LFSR to generate pattern for BIST applications with reduced power requirement.  ...  Here we discussed modified Test-per-Scan scheme [6] , which is based on Low Transition Random Pattern Generator (LT-PRG).  ... 
doi:10.5120/15285-3924 fatcat:ztb3lo3fhbcezf3htqyddqlwdm

Strategies and Techniques for Optimizing Power in BIST: A Review

Amandeep Singh, P. Mohan Kumar, Mohinder Bassi
2014 International Journal of Computer Applications  
Built in self test (BIST) and scan-based BIST are the techniques used for testing and detecting the faulty components in the VLSI circuit.  ...  Linear Feedback Shift Register (LFSR) in BIST generates pseudo-random patterns for detecting the faults, increasing the power consumption during testing, boosting the need to add power optimizations to  ...  So designing a Low Transition Low Power BIST for testing activity eliminates the need of external equipment for testing and reduces the power dissipation in test mode.  ... 
doi:10.5120/14976-3175 fatcat:pg7rprxbmngghg477zkegneh6e

Implementation of Low Power Circuit Analysis with Applications of Test Vectors

Ganesh Kumar M, Raja Sekhar S, Mahaboob Basha M
2015 IJIREEICE  
An advanced approach to design a fault coverage test pattern generator by utilizing linear feedback shift register called Bit Swap-LFSR.  ...  The main purpose of having intermediate patterns is to minimize the transitional processing at initial inputs; this could minimize the switching activities at circuit under test.  ...  Other authors propose two other low-power approaches for scan-based BIST.  ... 
doi:10.17148/ijireeice.2015.31235 fatcat:h7bzcza2hjhjtmdxbfdzbygdd4

An Efficient Technique to Reduce Average and Peak Power in Scan Based BIST

K. Thilagavathi, S. Sivanantham
2016 Indian Journal of Science and Technology  
Objectives: A low-transition Test Pattern Generator (TPG) known as Bit Swapping LFSR (BS-LFSR) which generates the test vectors with low transitions.  ...  The Weighted Transition Metric (WTM) is calculated after shifting of test patterns into the scan cells. Based on WTM values for each test pattern, scan cells are reordered to reduce the test power.  ...  Scan Based BIST For external Scan Based testing, Automatic Test Equipment is commonly used. ATE is becoming very expensive and its cost is increasing linearly in the present scenario.  ... 
doi:10.17485/ijst/2016/v9i38/102135 fatcat:qjgutqnclvedbmgl3cyrafehoy

Low-Transition Test Pattern Generation for BIST-Based Applications

Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
2008 IEEE transactions on computers  
LT-LFSR is independent of circuit under test and flexible to be used in both BIST and scan-based BIST architectures.  ...  A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during test by reducing the transitions  ...  Many low-power strategies have been proposed for full-scan [21] , [22] and BIST/scan-based BIST architectures [17] , [18] , [19] , [20] .  ... 
doi:10.1109/tc.2007.70794 fatcat:tm5pgeck6namtjn7uuvxxjcsfm

A Low Power BIST TPG for High Fault Coverage

R. Varatharajan, Lekha R.
2012 International Journal of Information Engineering and Electronic Business  
The proposed BIST comprised of three TPGs: Low transition random TPG (LT-RTPG), 3weight weighted random BIST (3-weight ERBIST) and Dual-speed LFSR (DS-LFSR).  ...  A low hardware overhead scan based BIST test pattern generator (TPG) that reduces switching activities in circuit under test (CUTs) and also achieve very high fault coverage with reasonable length of test  ...  CONCLUSION This paper proposes and presents a low hardware overhead test pattern generator (TPG) for a scan based BIST that can reduce SA in CUTs during BIST and also achieve very high fault coverage with  ... 
doi:10.5815/ijieeb.2012.04.03 fatcat:2av6wpwhezdjzil32ogke6jlsy

Design and Testing of 16 bit Carry Save Adder using Reconfigurable LFSR

2020 International Journal of Advanced Trends in Computer Science and Engineering  
The ever increasing applications of integrated circuits in the day-to-day useful electronic gadgets are the driving force for the development of low power designs of configurable hardware designs.  ...  Mobile applications have increased the technological improvements for digital signal processing applications.  ...  So these polynomials are fed to LFSR in logic BIST applications.  ... 
doi:10.30534/ijatcse/2020/156952020 fatcat:fg4znbugd5gbpb2izyvea2ejta

Low Power and High Fault Coverage BIST TPG

K. Vasudevareddy
2013 IOSR Journal of Engineering  
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based Built-In Self-Test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve  ...  Experimental results also show that the proposed BIST can be implemented with low area overhead.  ...  CONCLUSION This paper presents a low hardware overhead TPG for scan based BIST that can reduce switching activity in cuts during BIST and also achieve very high fault coverage with a reasonable length  ... 
doi:10.9790/3021-03511117 fatcat:hn3crd4uazbwhla3cxa65lmj5u

A BIST TPG for Low Power Dissipation and High Fault Coverage

R. Madhusudhanan, R. Balarani
2009 International Journal of MC Square Scientific Research  
This paper presents a low hardware overhead test pattern generator (TPG) for scan-based built-in self-test (BIST) that can reduce switching activity in circuits under test (CUTs) during BIST and also achieve  ...  Index Terms-Built-in self-test (BIST), heat dissipation during test application, low power testing, power dissipation during test application, random pattern testing.  ...  CONCLUSION This paper presents a low hardware overhead TPG for scan-based BIST that can reduce switching activity in CUTs during BIST and also achieve very high fault coverage with a reasonable  ... 
doi:10.20894/ijmsr.117.001.001.002 fatcat:gyqnwitwuzdcdeugpg6ddcc4ai

An Efficient Implementation of Built in Self Diagnosis for Low Power Test Pattern Generator

N. Nithya
2015 International Journal of Students Research in Technology & Management  
Modifications in Linear Feedback Shift Register to generate test pattern with security for modified Built-In-Self-Test applications with reduced power requirement.  ...  Architecture advantage is all data, which is relevant for a subsequent diagnosis, is gathered during just one test session.  ...  Logic BIST Architecture ARCHITECTURE OF BS-LFSR Bit-Swapping LFSR is based on some observations depending upon number of transition produced by LFSR at the output.  ... 
doi:10.18510/ijsrtm.2015.326 fatcat:ahrapsezqrhlje63mbadxyyqzu

Implementation of Low Power TPG using LFSR and single input changing generator (SICG) for BIST Application: A Review

Namratha M R, Jyothi Pramal, Praveen J, Raghavendra A Rao
2015 IJIREEICE  
A novel test pattern generator which is more suitable for built in self test (BIST) structures used for testing of VLSI circuits.  ...  In this approach, the single input change patterns generated by a counter and a gray code generator are Exclusive-ORed with the seed generated by the low power linear feedback shift register [LP-LFSR].  ...  Mehrdad Nourani, Mohammad Tehranipoor [3] presented their research work on Low-Transition Test Pattern Generation for BIST-Based Applications.  ... 
doi:10.17148/ijireeice.2015.3429 fatcat:36upg5ss4rfwvltaxo4cgvo2xa

A low cost test pattern generator for test-per-clock BIST scheme

Shaochong Lei, Zhen Wang, Zeye Liu, Feng Liang
2010 IEICE Electronics Express  
This paper proposes a low cost test pattern generator (TPG) for test-per-clock built-in self-test (BIST) scheme.  ...  The proposed method utilizes a two-dimensional TPG and a bit-XOR array to reduce area overhead, and generates single input change (SIC) sequences to reduce input transitions of the circuit under test (  ...  More advanced techniques have been widely studied and applied for testper-scan BIST scheme [2] . However, there are several approaches for testper-clock BIST applications.  ... 
doi:10.1587/elex.7.672 fatcat:zfzdhd5n3rc2deyhcadluumwf4

MULTI-DEGREE SMOOTHER FOR LOW POWER TESTABLE DIGITAL SYSTEM DESIGN USING BS-LFSR AND SCAN-CHAIN ORDERING TECHNIQUES

V. SURYANARAYANA, K. MIRANJI
2014 International Journal of Electronics Signals and Systems  
The first proposed technique, called bit-swapping LFSR (BS-LFSR), uses new observations concerning the output sequence of an LFSR to design a low-transition test-pattern-generator (TPG) for test-per-clock  ...  Another technique that aims to reduce peak power in scan-based BIST is presented.  ...  Average Power Minimization in Test-per-Scan BIST using Low Transition LFSR 3 Scan and Capture Peak Power Minimization in Scan-Based BIST using BS-LFSR, and 2-Phase Scan-Chain Ordering Algorithm 4.  ... 
doi:10.47893/ijess.2014.1193 fatcat:2vratke5ivhvjei2mlvnzkom5m

Survey of Low Power Testing of VLSI Circuits

P. Basker
2013 Science Journal of Circuits Systems and Signal Processing  
This paper surveys about the available low power testing techniques during testing. It also suggests some advantages and disadvantages associated with every techniques.  ...  On the other hand, a TPG for low power consumption in scan-based BIST (test-per-scan BIST) is presented in [6] .  ...  BIST or inside the scan-chain for scan-based BIST.  ... 
doi:10.11648/j.cssp.20130202.15 fatcat:bqr2cde4hndmznp52ajg4rlyku
« Previous Showing results 1 — 15 out of 403 results