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A single chip HBT power amplifier with integrated power control

David S. Ripley
2013 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)  
The GSM power amplifier market continues to drive towards low cost and small size, but remains reluctant to compromise on performance.  ...  The resulting solution opens opportunity for industry leading size and performance at no additional cost or RF performance penalty. Index Terms -power control, power amplifiers.  ...  ACKNOWLEDGEMENT The author wishes to acknowledge the assistance and support of Hongxiao Shao for PDK development, Pete Zampardi for process and modeling, Phil Lehtola for RF PA and module design, and Robert  ... 
doi:10.1109/rfic.2013.6569598 fatcat:dx75zgzdkvdyrlqwbnbcl7r5de

Dual-VT SRAM cells with full-swing single-ended bit line sensing for high-performance on-chip cache in 0.13 μm technology generation

Fatih Hamzaoglu, Yibin Te, Ali Keshavarzi, Kevin Zhang, Siva Narendra, Shekhar Borkar, Mircea Stan, Vivek De
2000 Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00  
Comparisons among different dual-V T design choices for a large on-chip cache with single-ended sensing show that the design using a dual-V T cell and low-V T peripheral circuits is the best, and provides  ...  10% performance gain with 1.2x larger active leakage power, and 1.6% larger cell area compared to the best design using high-V T cells.  ...  ACKNOWLEDGEMENTS The authors would like to thank Dick Hofsheier, Wenliang Chan, Ken Hose and Cheng-Feng Chang of Intel and Stephan Tang of UC, Berkeley for their encouragement and support for this work  ... 
doi:10.1145/344166.344182 fatcat:6q4z7aw36nfqpcusoej3rw4xe4

A Low-Power Low-Swing Single-Ended Multi-Port SRAM

Hao-I Yang, Ming-Hung Chang, Ssu-Yun Lai, Hsiang-Fei Wang, Wei Hwang
2007 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)  
A single-ended current-mode sensing amplifier is also presented. This amplifier can sense a very small swing of bitline, equipping with a high noise-rejection and high PVT-tolerance ability.  ...  In this paper, a new single-ended 6-T SRAM cell is proposed. It has a very strong static noise margin (SNM) during read cycles.  ...  As is designed to overcome this challenge. multi-core SoC plays a significant role, high density and low For a traditional single-ended 5-T SRAM, the bitline wordline switching power design is attractive  ... 
doi:10.1109/vdat.2007.373203 fatcat:ox2dwltr5vdsnne4vpdm363vsa

A comparative analysis of optimized CMOS neural amplifier

Ahmed El-Attar, Saif Ahmed, Youssef Abdelkader, Mohamed Badran, Ali H. Hassan, Hassan Mostafa
2015 2015 27th International Conference on Microelectronics (ICM)  
This paper investigates various implementation techniques of neural amplifiers with emphasis on their design performance metrics and trade-offs such as gain, noise, power consumption, and area.  ...  The proposed comparative analysis covers the recently published neural amplifiers in the literature, and proposes a basic optimization method for these amplifiers.  ...  feedback LNA, single stage amplifier, the telescopic OTA has been replaced by current re-use OTA for lower power consumption, and better noise performance as shown is shown in Table I . o For the single  ... 
doi:10.1109/icm.2015.7437999 dblp:conf/icm2/El-AttarAABHM15 fatcat:z5w4o3awwjguhkurf4dgnq5rbq

Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories

Igor Arsovski, Reid Wistort
2006 IEEE Custom Integrated Circuits Conference 2006  
When compared to conventional single-ended sensing, this method reduces sense time by 70% and decreases sense-power by 40%.  ...  A memory sense-amplifier self-calibrates during sense-line precharge to reduce the required signal development and minimize data capture timing uncertainty caused by random device variation.  ...  Nadkarni, H.Pilo, and J. Oppold for insightful discussions, M. Willete for hardware testing, M. Ziegerhofer and M. Lestrange for technical editing, and M. Boudreaux, J. Chickanosky, and M.  ... 
doi:10.1109/cicc.2006.320819 dblp:conf/cicc/ArsovskiW06 fatcat:h3sto65klzbfvplgfa642i5idi

A Comparative Study of Interconnect Circuit Techniques for Energy Efficient On-Chip Interconnects

C. Venkataiah, M. Tejaswi
2015 International Journal of Computer Applications  
Interconnects in high speed applications suffer from crosstalk, signal delay and ground noise, causing degradation of system performance.  ...  All the circuits are simulated and compared different parameters such as power, delay and energy by using micro wind in 45nm technology.  ...  Single ended sensing has been explored for crossbars and on chip interconnects.  ... 
doi:10.5120/19180-0658 fatcat:a2ovybjzzvhjdnklyjyzoxqism

A compact low-power nonvolatile flip-flop using domain-wall-motion-device-based single-ended structure

Daisuke Suzuki, Noboru Sakimura, Masanori Natsui, Akira Mochizuki, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu
2014 IEICE Electronics Express  
In fact, the area and the power-delay product of the proposed NV-FF are minimized compared to those of the previous works.  ...  Moreover, the use of a nonvolatile storage cell with a DWM-device-based single-ended structure makes it possible to implement both of these functions as two CMOS inverters, which makes it possible to merge  ...  ", initiated by the Council for Science and Technology Policy (CSTP).  ... 
doi:10.1587/elex.11.20140296 fatcat:slbqpiz52nhbndeqgkkftkzbfy

A 125μW 8kS/s Sub-pA Area-Efficient Current Sensing 45nm CMOS ADC for Biosensing [article]

Mitra Saeidi, Luke Theogarajan
2021 arXiv   pre-print
Our approach combines the transimpedance amplifier (TIA) and ADC into a unified structure by folding a low-noise capacitive TIA into the first stage integrator of a 2nd order Delta-Sigma modulator.  ...  This paper presents a 125μW, area efficient (0.042mm2) 81dB DR, 8kS/s current sensing ADC in 45nm CMOS capable of sensing sub-pA currents.  ...  Introduction Single-molecule electronic biosensors require high-precision current sensing (~1pA) with high bandwidth (>1kHz) and dynamic range (>10b).  ... 
arXiv:2107.05794v1 fatcat:mvbyw4upynhyrmdywpngktpx5e

Low-power low-noise analog circuits for on-focal-plane signal processing of infrared sensors

Bedabrata Pain, Sunetra K. Mendis, Robert C. Schober, Robert H. Nixon, Eric R. Fossum, Albert M. Fowler
1993 Infrared Detectors and Instrumentation  
The design of low-power (< 5 xW), sub-electron input-referred noise, high-gain (> 100,000), small real-estate (60 p.m pitch) self-biased CMOS amplifiers required for photon counting are presented. 0-8194  ...  For improving the performance of low-background [R imagers, an on-chip column-parallel analog-to-digital converter (ADC) is presented.  ...  Aeronautics and Space Administration.  ... 
doi:10.1117/12.158688 fatcat:5nxdwoqblvdklgjkannkqvx6ny

Adiabatic 5T SRAM

Mamatha Samson, Satyam Mandavalli
2011 2011 International Symposium on Electronic System Design  
This energy efficient SRAM also provides good performance parameters and hence suitable for high density embedded systems.  ...  The energy recovery driver saves energy in the single bit line in addition to enhancing the write ability of the 5T SRAM.  ...  A low-power SRAM using hierarchical bit-line and local sense-amplifiers (HBLSASRAM) has been reported to reduce write power consumption in bit-lines [2] .  ... 
doi:10.1109/ised.2011.57 dblp:conf/ised/SamsonM11 fatcat:olakezwaijgljihr6c4w6gibha

A Low-Power Switched-Capacitor Capacitive Transducer With High Resolution

Xiaoling Zhang, P.K. Chan
2008 IEEE Transactions on Instrumentation and Measurement  
A Low-Power Switched-Capacitor Capacitive Transducer With High Resolution Xiaoling Zhang and P. K.  ...  The low-power design strategy combined with the chopper-stabilized fully differential op-amp and the CHSDDA has achieved low-power consumption, high resolution, and low noise.  ... 
doi:10.1109/tim.2008.917680 fatcat:enjardmr3vcbjm27vlbhi3hjba

Chopper Stabilized, Low-Power, Low-Noise, Front End Interface Circuit for Capacitive CMOS MEMS Sensor Applications

Nebyu Yonas Sutri, John Ojur Dennis, Mohd Haris Md Khir, Muhammad Umer Mian, Tong Boon Tang
2013 Modern Applied Science  
In this paper, a chopper stabilized fully differential CMOS pre-amplifier circuit is presented. The proposed circuit is designed for sub-atto Farad capacitive CMOS MEMS sensing applications.  ...  Chopper stabilization technique is employed to minimize flicker (1/f) noise and offsets in the circuit.  ...  ., 2010) showed that using only a single stage amplifier for the interface circuitry to achieve both low noise and low power requirements is a challenging task.  ... 
doi:10.5539/mas.v7n12p34 fatcat:3gcc4xfw6za37n62sxq2vz4jbm

Non-contact Low Power EEG/ECG Electrode for High Density Wearable Biopotential Sensor Networks

Yu M. Chi, Stephen R. Deiss, Gert Cauwenberghs
2009 2009 Sixth International Workshop on Wearable and Implantable Body Sensor Networks  
The coin sized electrode consumes 285µA from a single 3.3V supply, and interfaces with a serial data bus for daisychain integration in body area sensor networks. 2009 Body Sensor Networks 978-0-7695-3644  ...  Each electrode senses the local biopotential with a differential gain of 46dB over a 1-100Hz bandwidth. Signals are digitized directly on board with a 16-bit ADC.  ...  v i s = C i s C i s + C i in v i . (1) Although the FET input amplifier (LT6078) provides low noise operation at low power consumption with high input impedance and low input capacitance, it requires  ... 
doi:10.1109/bsn.2009.52 dblp:conf/bsn/ChiDC09 fatcat:y4jeb2rr5bcwjnv3rucxokr3lu


Wei Cai, Cheng Li, Heng Gu
2016 International Journal of Pharmacy and Pharmaceutical Sciences  
The ultimate goal for such application is to minimize the trade-offs between performance and cost, and between performance and low power consumption design.  ...  This class B power amplifier could transmit 26dBm output power to a 50Ω load. The power added efficiency was 60% minimum and the power gain was 90dB, the total power consumption was 6.9 mW.  ...  This singled ended class B power amplifier design simultaneously achieves high power added efficiency (PAE) and high third-order intermodulation (IM3) suppression.  ... 
doi:10.22159/ijpps.2016v8i9.12141 fatcat:q74p65coenbftdwkvxulvr4wum

Session 24 Overview: Advanced Embedded Memories

Eric Karl, Shinichiro Shiratake, Jonathan Chang
2021 2021 IEEE International Solid- State Circuits Conference (ISSCC)  
This session details recent advancements in SRAM and RRAM technology and circuits. The first paper describes an ultra-high-performance and low-power sensing technique for single-ended 8T SRAM arrays.  ...  The final paper outlines a standard-cell based SRAM design for small macros: demonstrating high-performance and ultra-low operating voltages.  ...  This session details recent advancements in SRAM and RRAM technology and circuits. The first paper describes an ultra-high-performance and low-power sensing technique for single-ended 8T SRAM arrays.  ... 
doi:10.1109/isscc42613.2021.9365820 fatcat:icsmynafhfdqhehzioy2qhzyru
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