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Low Power Mixed-Signal SoC Integration and Verification Challenges with Third Party IP Cores

Ruchi Shankar, Prachi Mishra, Abhinav Parashar, Ashwini Padoor, Lakshmanan Balasubramanian
2019 EAI Endorsed Transactions on Cloud Systems  
Integrating third party IP core typically involves various challenges.  ...  These challenges involve compatibility with power, reset and clock (PRC) schemes, design methods used to achieve system low power goals, integration scalability, and design verification methods to achieve  ...  Subramonia, Rajesh Kumar Mittal, Maneesh Soni (Ex-TI) , Rajeev Suvarna, Thomas Trinkwalder, Harish Maruthiyodan, Arif Mohammed, Jaya Singh Texas Instruments Inc. for their consistent motivation, opportunity and  ... 
doi:10.4108/eai.5-11-2019.162592 fatcat:mvhtnkr6rfhszmnei4rbnbdmvm

System-on-Chip: Reuse and Integration

R. Saleh, S. Wilton, S. Mirabbasi, A. Hu, M. Greenstreet, G. Lemieux, P.P. Pande, C. Grecu, A. Ivanov
2006 Proceedings of the IEEE  
Design-for-test methodologies are also described, along with verification issues that must be addressed when integrating reusable components.  ...  (SoC) design.  ...  The authors also wish to thank the Canadian Microelectronics Corporation (CMC) for licensing the infrastructure used in this work, and for invaluable discussions regarding SoC design and reuse.  ... 
doi:10.1109/jproc.2006.873611 fatcat:tfwuk4abpjemfec6aswc23orfu

2003 technology roadmap for semiconductors

D. Edenfeld, A.B. Kahng, M. Rodgers, Y. Zorian
2004 Computer  
The 2003 ITRS system drivers chapter presents an overarching SoC context for future semiconductor products, along with new discussions of technology requirements for analog/mixed-signal and embedded memory  ...  These models support extrapolation of future technology requirements for basic circuit fabricsprocessor, analog/mixed-signal, and embedded memory-as well as the SoC products they comprise.  ...  However, when IP is purchased or licensed from a third party, it is typically the test methodology that must adapt.  ... 
doi:10.1109/mc.2004.1260725 fatcat:eqstk5zzbzfkbl6upd2jjc4f4m

Call for Papers

2006 7th International Symposium on Quality Electronic Design (ISQED'06)  
Design and synthesis of high complexity ICs: signal integrity, transmission line effects, OPC, phase shifting, and sub-wavelength lithography, manufacturing yield and technology capability.  ...  Design metrics, methodologies and flows for custom, semi-custom, ASIC, FPGA, RF, memory, networking circuit, etc. with emphasis on quality. Design metrics and quality standards for SoC, and SiP.  ...  Challenges and solutions of the integration, testing, and qualifying of IP blocks from multiple vendors. Third party testing of IP blocks. Risk management of IP reuse.  ... 
doi:10.1109/isqed.2006.32 fatcat:fnsiegfjcrb4lhgwqogh64kbq4

System Level Modelling of Reconfigurable FFT Architecture for System-on-Chip Design

A. Ahmadinia, B. Ahmad, T. Arslan
2007 Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)  
This paper aims to produce new high level IP models in SystemC for functional verification of IP integrations, incorporating both embedded custom reconfigurable and conventional IPs, which are optimised  ...  in terms of IP Core parameters.  ...  Our methodology is to deal with hybrid SoC systems which include custom reconfigurable IP cores, conventional parameterisable IP cores, interconnected using mixed interconnection schemes which are not  ... 
doi:10.1109/ahs.2007.102 dblp:conf/ahs/AhmadiniaAA07 fatcat:mfefwnjzxnfybcg77t7vdq26pi

Panel: Future SoC verification methodology: UVM evolution or revolution?

Rolf Drechsler, Christophe Chevallaz, Franco Fummi, Alan J. Hu, Ronny Morad, Frank Schirrmeister, Alex Goryachev
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014  
With increasing design complexity System on Chip (SoC) verification is becoming a more and more important and challenging aspect of the overall development process.  ...  In this panel leading experts from industry (both users and vendors) and academy will discuss the future of SoC verification methodology.  ...  Another wild subject of interest is the link between formal and mixed Analog Signals. Address system verification The challenges of system verification are multiple.  ... 
doi:10.7873/date.2014.385 dblp:conf/date/DrechslerCFHMSG14 fatcat:ydgn5xjetrhmziuum4qlfzdtpi

Towards an Ontology-driven Intellectual Properties reuse for Systems On Chip design

Fateh Boutekkouk
2021 International journal of computers and communications  
However the need for a standard representation that permits IPs classification, characterization, and integration is still a big challenge.  ...  To address this problem, we propose to develop an IPs reuse specific ontology that facilitates IPs reuse at many levels of abstraction and independently from any design language or tool.  ...  Such a solution can decrease the implementation cost and the power consumption but in the same time it faces a big challenge with regard to the effort of design including verification cost and time-to-market  ... 
doi:10.46300/91013.2021.15.13 fatcat:uyfpnfksv5f6rd26qatva23pi4

Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture

Jagadeesh Kokila, Arjun Murali Das, Basha Shameedha Begum, Natarajan Ramasubramanian
2019 Periodica Polytechnica Electrical Engineering and Computer Science  
The results were obtained with the help of three Intellectual Property (IP) cores – Zedboard OLED IP, ISCAS'89 s1423 Benchmark IP and a Full Adder IP.  ...  Major issues include hardware Trojan attack, hardware intellectual property (IP) theft, such as an illegal sale or use of firm intellectual property cores or integrated circuits (ICs) and physical attacks  ...  A third-party IP core vendor can sell an IP core as their own without even knowing the internal architecture or implementation.  ... 
doi:10.3311/ppee.13424 fatcat:gha4aoeqcbba3hxu7iwu6y3lmq

Introduction to Hardware Security

Yier Jin
2015 Electronics  
However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware.  ...  To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures  ...  Following this trend, third-party resources in hardware circuit designs, mostly in the format of third-party fabrication services and third-party soft/hard IP cores for SoC development, are prevailingly  ... 
doi:10.3390/electronics4040763 fatcat:njdmrvdogzc73mp4yun6rpnun4

Hardware Trojans

K. Xiao, D. Forte, Y. Jin, R. Karri, S. Bhunia, M. Tehranipoor
2016 ACM Transactions on Design Automation of Electronic Systems  
., malicious modifications or inclusions made by untrusted third parties) pose major security concerns, especially for those integrated circuits (ICs) and systems used in critical applications and cyber  ...  Then the past countermeasures and publication trends are categorized based on the adversarial model and topic.  ...  They integrate some IP cores from 3PIP vendors into their SoC designs and fabricate these chips in untrusted third-party foundries.  ... 
doi:10.1145/2906147 fatcat:24ffmzsrnbgkrkjq3ooztg4fbe

The TI OMAP™ Platform Approach to SOC [chapter]

Peter Cumming
2003 Winning the SoC Revolution  
We conclude with a detailed description of the TI Wireless SoC platform.  ...  Platform-based design of SoC, as practiced by Texas Instruments, has two key characteristics: platforms are defined hierarchically and software plays as critical a role as hardware.  ...  third party collaboration.  ... 
doi:10.1007/978-1-4615-0369-9_5 fatcat:rj6qo6iggnct7noi6pff7ioj4i

Current Status of the Integrated Circuit Industry in China ― EDA Industry Review

Litho World
2019 Journal of Microelectronic Manufacturing  
It could meet requirements of modern users, which is low power consumption and high performance. It could solve the IC designer's problem of design and verification of mixed signal circuits.  ...  It can seamlessly integrate the SPICE simulation tools ALPS-AS and layout verification tool Argus of Empyrean Software, it can also be integrated other tools from the third party.  ... 
doi:10.33079/jomm.19020305 fatcat:whomlgrm4jejnp4pyegw7p3dhu

A PUF-based cryptographic security solution for IoT systems on chip

Alexandra Balan, Titus Balan, Marcian Cirstea, Florin Sandu
2020 EURASIP Journal on Wireless Communications and Networking  
The integration of multicore processors and peripherals from multiple intellectual property core providers as hardware components of IoT multiprocessor systems-on-chip (SoC) represents a source of security  ...  This paper describes the concept and the practical results of a SoC security implementation that is illustrative for IoT applications.  ...  Acknowledgements The authors would like to thank the members of the COST Action CA15104 IRACON, "Inclusive Radio Communication Networks for 5G and Beyond, " for their valuable advice and guidance related  ... 
doi:10.1186/s13638-020-01839-6 fatcat:okq5soehg5atfj52zozazvt22i

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism

Mohamed Elshamy, Giorgio Di Natale, Antonios Pavlidis, Marie-Minerve Louerat, Haralampos-G. Stratigopoulos
2020 2020 IEEE European Test Symposium (ETS)  
This HT attack cannot be detected or prevented in the analog domain and it exploits the dense digital circuit to hide effectively its footprint.  ...  Instead, it resides on an independent digital circuit on the same die where it is triggered, yet its payload is applied only to the analog circuit after being transferred via the common test infrastructure and  ...  ACKNOWLEDGMENTS This work has been carried out in the framework of the ANR STEALTH project with N o ANR-17-CE24-0022-01.  ... 
doi:10.1109/ets48528.2020.9131560 dblp:conf/ets/ElshamyNPLS20 fatcat:q66f7pb4tzdnlm64wnomkg3w4e

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards [article]

Rajeev Muralidhar and Renata Borovica-Gajic and Rajkumar Buyya
2020 arXiv   pre-print
These trends continue, arguably with other limits, along with challenges imposed by tighter integration, extreme form factors and diverse workloads, making systems more complex from an energy efficiency  ...  parallelism (ILP) and the end of Dennard's scaling drove the industry towards multi-core chips.  ...  Since SOCs typically integrate third party IP blocks, specific PM related tests are needed for such IPs.  ... 
arXiv:2007.09976v2 fatcat:enrfj2qgerhyteapwykxcb5pni
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