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Loose loops sink chips

E. Borch, E. Tune, S. Manne, J. Emer
Proceedings Eighth International Symposium on High Performance Computer Architecture  
A new loose loop is introduced into the pipeline by the DRA, but the frequency of mis-speculations is very low.  ...  In particular, we establish the relationship between loose loops and pipeline length and configuration, and show their impact on performance.  ...  It is this unknown that necessitates a loose loop. As with all loose loops, the pipeline could either stall or speculate.  ... 
doi:10.1109/hpca.2002.995719 dblp:conf/hpca/BorchTME02 fatcat:ievh5c4qobdjlnsigmkpkbra3u

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Anders Björner, László Lovász
2012 Journal of Algebraic Combinatorics  
A move consists of selecting a node with at least as many chips as its outdegree, and sending one chip along each outgoing edge to its neighbors.  ...  We consider the following (solitary) game: each node of a directed graph contains a pile of chips.  ...  Loops and multiple edges are allowed.  ... 
doi:10.1023/a:1022467132614 fatcat:bebrna6razhjtffzl3m2vvqzie

Poems

Kate Hargreaves
2013 Canada and Beyond: A Journal of Canadian Literary and Cultural Studies  
She misses.She sinks her face into her towel.She collects stray hairs from the bathroom sink.She scrimps by the skin of her teeth.She teethes.She sinks her teeth into a stale bread roll.She stinks of garlic  ...  Elle unties the cord on her robe yesterday she finished reading a novel that called it a housecoat robe, yes, but something about housecoat less regal, explains the bite marks and loose threads from where  ... 
doi:10.33776/candb.v3i1-2.3054 fatcat:ytyi4ovrhfdmdjvmlyuljlyyce

Rotor-routing reachability is easy, chip-firing reachability is hard [article]

Lilla Tóthmérész
2021 arXiv   pre-print
Here we show that in the general case, chip-firing reachability is hard in the sense that if the chip-firing reachability problem were in P for general digraphs, then the polynomial hierarchy would collapse  ...  Chip-firing and rotor-routing are two well-studied examples of Abelian networks. We study the complexity of their respective reachability problems.  ...  Moreover, v can only loose chips by routings, and it cannot go negative by a legal routing. Hence after its first routing, v always has a nonnegative number of chips, thus, y(v) ≥ 0.  ... 
arXiv:2102.11970v1 fatcat:6o4of77nzjbkbmuxuvskeaex3e

Direct synthesis of optimized DSP assembly code from signal flow block diagrams

D.B. Powell, E.A. Lee, W.C. Newman
1992 [Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing  
In the Motorola DSP56001, one on-chip instruction and two on-chip data words can be accessed in parallel, while there is only one external memory interface.  ...  Also, loop overhead -in terms of code size -is independent of the amount of repetition involved in the loop.  ... 
doi:10.1109/icassp.1992.226560 dblp:conf/icassp/PowellLN92 fatcat:ea5x2rb2erhtfczt3wzaggrzby

SPEED CONTROL OF THREE-PHASE INDUCTION MOTOR DRIVE

Salah Ramadan, Ramadan Mostafa, Aiman Youssef
1991 International Conference on Aerospace Sciences and Aviation Technology  
It was strongly required, that the design and implementation of the control and logic circuits must be cheap and simple as possible without loosing the stability of the system.  ...  These two types are connected in economical way in which each one transistor and its complement are placed on one heat sink.  ...  The six pulses Ql to Q6 are passing through a buffer chip (TTL 7404) to obtain the sufficient current required to drive the next six AND gates (TTL 7402 chip).  ... 
doi:10.21608/asat.1991.25849 fatcat:ces5jqg7xfatbljao2mnxpszoy

Page 447 of Peterson Magazine Vol. 65, Issue 6 [page]

1874 Peterson Magazine  
Fio 1—Wa.xine-Dress or Licut-Mournine or, Buack asp Waite Stripep Sink.  ...  White chip bonnet, trimmed with blue velvet rib- bon at the back, blue convolvulus, and a white rose. Vig. 111.  ... 

An Efficient Parallel Gauss-Seidel Algorithm on a 3D Torus Network-on-Chip

Khaled Day, Mohammad H. Al-Towaiq
2015 Sultan Qaboos University Journal for Science  
Network-on-chip (NoC) multi-core architectures with a large number of processing elements are becoming a reality with the recent developments in technology.  ...  sink row.  ...  Therefore the proposed parallel GS algorithm runs faster on a NoC than on a loosely coupled cluster or a tightly coupled multiprocessor.  ... 
doi:10.24200/squjs.vol20iss1pp29-38 fatcat:wjarxsrxwrgwlc22l5uvc63mfq

Temperature-aware computer systems: opportunities and challenges

K. Skadron, M.R. Stan, Wei Huang, S. Velusamy, K. Sankaranarayanan, D. Tarjan
2003 IEEE Micro  
Low-power, low-cost chips often omit the heat spreader and sometimes even the heat sink. Mobile devices often use heat pipes and other packaging that avoids the weight and size of a heat sink.  ...  The table shows that IPC and peak operating temperature only loosely correlate with average power dissipation.  ... 
doi:10.1109/mm.2003.1261387 fatcat:bm2zzlxamrcj7an2cpjfcrf7i4

Computer-aided design for microfluidic chips based on multilayer soft lithography

Nada Amin, William Thies, Saman Amarasinghe
2009 2009 IEEE International Conference on Computer Design  
The first chip ( Figure 6 ) performs a cell culture of a large embryonic cell, with a recirculation loop and sample extraction [22] .  ...  In addition to points on the actual flow layer, each chip contains an abstract source point and sink point which should be considered to reside off-chip.  ... 
doi:10.1109/iccd.2009.5413185 dblp:conf/iccd/AminTA09 fatcat:htngzpeyzfe7pi5vusiyovf2mi

A Low-Power Blocking-Capacitor-Free Charge-Balanced Electrode-Stimulator Chip With Less Than 6 nA DC Error for 1-mA Full-Scale Stimulation

Ji-Jon Sit, Rahul Sarpeshkar
2007 IEEE Transactions on Biomedical Circuits and Systems  
On +6 and 9 V rails in a 0.7-m AMI high voltage process, the power consumption of a single channel of this chip is 47 W when biasing power is shared by 16 channels.  ...  We describe an electrode-stimulator chip that removes the need for large dc blocking capacitors in neural implants by achieving precise charge-balanced stimulation with 6 nA of dc error.  ...  determined by the resistivity of the fluid (set by ionic species in solution). is the double-layer capacitance, created by the accumulation of tightly adsorbed ions at the electrode surface and more loosely  ... 
doi:10.1109/tbcas.2007.911631 pmid:23852411 fatcat:vevkw3lnhjh7xbby6rvwla3try

A Wireless Implantable Multichannel Microstimulating System-on-a-Chip With Modular Architecture

M. Ghovanloo, K. Najafi
2007 IEEE transactions on neural systems and rehabilitation engineering  
A 64-site wireless current microstimulator chip (Interestim-2B) and a prototype implant based on the same chip have been developed for neural prosthetic applications.  ...  Modular standalone architecture allows up to 32 chips to be individually addressed and operated in parallel to drive up to 2048 stimulating sites.  ...  sink in Mode-3.  ... 
doi:10.1109/tnsre.2007.903970 pmid:17894278 fatcat:fk2l3jpmtvcxnp5dqsiu5pjgb4

Analytical bound for unwanted clock skew due to wire width variation

A. Rajaram, Bing Lu, Wei Guo, R. Mahapatra, Jiang Hu
2003 ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486)  
Impact from intra-chip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature.  ...  This is especially true when the intra-chip variations start to dominate the inter-chip variations [12] .  ...  Therefore, the corner-point technique is useful only when a loose bound needs to be found quickly.  ... 
doi:10.1109/iccad.2003.159718 fatcat:4wttmivgrngsnprqoyynikcc3y

Analytical bound for unwanted clock skew due to wire width variation

A. Rajaram, Bing Lu, Jiang Hu, R. Mahapatra, Wei Guo
2006 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Impact from intra-chip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature.  ...  This is especially true when the intra-chip variations start to dominate the inter-chip variations [12] .  ...  Therefore, the corner-point technique is useful only when a loose bound needs to be found quickly.  ... 
doi:10.1109/tcad.2005.857398 fatcat:u4lwgyfikrfrnlwmuiz22mul6e

Compositional Performance Verification of Network-on-Chip Designs

Daniel E. Holcomb, Sanjit A. Seshia
2014 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
INTRODUCTION Network on chip (NoC) is a paradigm for communication within large many-core system on chip (SoC) designs.  ...  Evaluating Looseness of T L with Bounded Model Checking The global age bound (T L ) that is implied by the age lemmas can be loose.  ... 
doi:10.1109/tcad.2014.2331342 fatcat:w4jg5dibtbagxoniwlizvsqxym
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