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Some Characteristics of the Referential and Inferential Predication in Classical Logic

Nijaz Ibrulj, Univeristy of Sarajevo, Faculty of Philosophy
2021 The Logical Foresight-Journal for Logic and Science  
Logic is characterized in different ways when it is associated with syllogistics (referential – semantical model of logic) or with symbolic logic (inferential – syntactical model of logic).  ...  In the article we consider the relationship of traditional provisions of basic logical concepts and confront them with new and modern approaches to the same concepts.  ...  represented in different types of semantic characterization and different hierarchies of structural characterization; By "thought objects of varying complexity" we mean the logical forms concept, judgment  ... 
doi:10.54889/issn.2744-208x.2021.1.1.1 fatcat:btgp4k4l5rgz3kmclj2qkfgcem

Page 2263 of Mathematical Reviews Vol. , Issue 94d [page]

1994 Mathematical Reviews  
William Gasarch (1-MD-C; College Park, MD) 94d:68040 68Q15 03D15 Stewart, Iain A. (4-NWCT-C; Newcastle upon Tyne) Logical and schematic characterization of complexity classes.  ...  This paper continues the work of Fagin and Immerman on the characterization of complexity classes by logical theories.  ... 

Page 1277 of Mathematical Reviews Vol. , Issue 91C [page]

1991 Mathematical Reviews  
It is shown that the introduced canonical semantics are complete and are equivalent for classes of functional dependencies, logics of implication and strong logics of implication.  ...  Closure systems, closure operators, the logic of implication, the strong logic of implications and classes of functional dependencies can be mapped each to another.  ... 

Bounded arithmetic, proof complexity and two papers of Parikh

Samuel R. Buss
1999 Annals of Pure and Applied Logic  
Parikh's work on feasibility, bounded arithmetic and the complexity of proofs.  ...  We discuss in depth two of Parikh's papers on these subjects and some of the subsequent progress in the areas of feasible arithmetic and lengths of proofs.  ...  logical complexity.  ... 
doi:10.1016/s0168-0072(98)00030-x fatcat:7etzlilxmrau3bsjceekfwms5y

High-Level Synthesis of Digital Circuits [chapter]

Giovanni De Micheli
1993 Advances in Computers  
A problem arises, however, when we try to conceive and enter the logic schematics of large-scale systems. This task is time-consuming, tedious, and error-prone.  ...  common way of entering a digital design is to use programs that capture the logic schematic.  ... 
doi:10.1016/s0065-2458(08)60406-4 fatcat:miay4gf7y5hrnldx6tl2gz4m5i

Page 4740 of Mathematical Reviews Vol. , Issue 94h [page]

1994 Mathematical Reviews  
Stewart, Logical characterizations of bounded query classes. I.  ...  real-time systems (81-92); Soren Chris- tensen [Seren Christensen*], A logical characterization of asyn- chronously communicating agents (93-104); Melvin Fitting, Many- valued nonmonotonic modal logics  ... 

Page 1116 of Mathematical Reviews Vol. , Issue 81C [page]

1981 Mathematical Reviews  
Valiev, On axiomatization of deterministic propositional dynamic logic (pp. 482-491); Klaus Wagner, Bounded recursion and complexity classes (pp. 492-498); Wolfgang Wechler, Characterization of ra- tional  ...  logic (pp. 381-389); Anton Nijholt and Eljas Soisalon-Soininen, Ch[k] grammars: a characterization of LL{k] languages (pp. 390-397); Th.  ... 

On the Concept of a Notational Variant [chapter]

Alexander W. Kocurek
2017 Lecture Notes in Computer Science  
In light of this, we will explore a weaker version of this notion that we will call schematicity and show that there is no schematic translation either from first-order logic to propositional logic or  ...  In the study of modal and nonclassical logics, translations have frequently been employed as a way of measuring the inferential capabilities of a logic.  ...  Let L 1 and L 2 be Σ 1 -and Σ 2 -logics respectively, and let T be a class of translations from L 1 to L 2 .  ... 
doi:10.1007/978-3-662-55665-8_20 fatcat:7zfeemwrmfa7tcn2ygft5eayye

Optimization of 1D and 2D Cellular Automata for Pseudo Random Number Generator

P Sudhakar, B Chinnarao, Dr. M. Madhavi Latha
2014 IOSR Journal of VLSI and Signal processing  
Rule 30 is an update rule that when applied to the CA will produce a class III, a periodic, chaotic behavior.  ...  The response with respect to rule 2 and rule 90 is also verified on Xilinx Spartan 3E FPGA and this can be applied for modeling PRNG.  ...  To characterize group and non group 2D CA and identify cycle length of 2D CA group rules and depth and inner cycle length of non group 2D CA.  ... 
doi:10.9790/4200-04612833 fatcat:wzlo64xgyvf2bmp7mqmfhd6zc4

Exploiting unified modelling language (UML) as a preliminary design tool for Common Logic-based ontologies in manufacturing

C. Palmer, N. Chungoora, R.I.M. Young, A.G. Gunendran, Z. Usman, K. Case, J.A. Harding
2013 International journal of computer integrated manufacturing (Print)  
Acknowledgements We wish to thank the EPSRC, who have funded the work behind this paper through two related digital manufacturing projects, project 253 and project 237, of the Loughborough University Innovative  ...  Manufacturing and Construction Research Centre.  ...  of Common Logic to model its inherent complexity, as indicated by the arguments above.  ... 
doi:10.1080/0951192x.2012.688142 fatcat:othyqrskxngmtfpvn2lwvrbp6q

The Neurophysiological Bases of Cognitive Computation Using Rough Set Theory [chapter]

Andrzej W. Przybyszewski
2008 Lecture Notes in Computer Science  
The FF pathways combine properties extracted in each area into a vast number of hypothetical objects by using "driver logical rules", in contrast to "modulator logical rules" of the FB pathways.  ...  Psychophysical experiments and our amazing capability to recognize complex objects (like faces) in different light and context conditions argue against symbolic representation and suggest that concept  ...  Thanks to Carmelo Milo for his technical help, as well to Farah Averill and Dana Hayward for their help in editing the manuscript.  ... 
doi:10.1007/978-3-540-89876-4_16 fatcat:uha2saitlzbgnjbwd3e6a3rnhy

ORIS: a tool for state-space analysis of real-time preemptive systems

G. Bucci, L. Sassoli, E. Vicario
2004 First International Conference on the Quantitative Evaluation of Systems, 2004. QEST 2004. Proceedings.  
The great expressiveness of these methods is counterbalanced by the increased complexity of the analysis, which may grow exponentially.  ...  In this paper we present Oris, an environment for building, simulating, analyzing and validating complex real time systems specified in terms of an extended TPN formalism, named Preemptive Time Petri Nets  ...  Since TPNs have a dense time semantics, in order to obtain a discrete enumeration of the statespace, individual states are collected into state classes each characterized by a logical location (i.e. a  ... 
doi:10.1109/qest.2004.1348021 dblp:conf/qest/BucciSV04 fatcat:ya5ycjkhvvgixps644benj2nee

Page 709 of Mathematical Reviews Vol. 54, Issue 3 [page]

1977 Mathematical Reviews  
Citing the aforementioned paper of Friedberg and Rogers, the author notes that the concept of c-reducibility and c,-reducibility differ on the class of re sets.  ...  The author presents a necessary and sufficient condition for a set A of natural numbers to be complete with respect to a schematically defined notion of reducibility.  ... 

Page 171 of Psychological Abstracts Vol. 42, Issue 2 [page]

1968 Psychological Abstracts  
Other classes can be obtained from the above. The logical relations of the signs are invariate with respect to concept categories. They determine its structure.  ...  Subsequent CI perform- ance and extinction phases showed: (1) progressively better Cl performance in low complexity-solvable set problems, (2) increase MAP with unsolvable set-high complexity Cl, and (  ... 

Validating PowerPC microprocessor custom memories

N. Krishnamurthy, A.K. Martin, M.S. Abadir, J.A. Abraham
2000 IEEE Design & Test of Computers  
Address Data in Read enable Write enable C1 clock Data in Read/write control logic Address decode logic Data conditioning logic Sense-amp outputs column MUX Figure 15. Custom memory.  ...  Acknowledgments We thank the entire project and tools teams at Somerset, Motorola, for their cooperation and commitment to the successful conclusion of this project.  ...  Previous authors have attributed complex timing, multiple clock phases, complex sequential control logic, and the large number of stateholding elements (state explosion) as their reason for using a simulation-based  ... 
doi:10.1109/54.895007 fatcat:t3w2vughyzem5ot2okcxnb43hm
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