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Logic filter cache for wide-VDD-range processors

Alen Bardizbanyan, Oskar Andersson, Joachim Rodrigues, Per Larsson-Edefors
2016 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS)  
Wide-VDD-range processors offer high energy efficiency for varying embedded workloads.  ...  We implement a data and instruction filter cache, using logic cells located in the CPU VDD domain, to permit the level-1 (L1) cache to be reliably powered at a higher SRAM VDD.  ...  filter caches for wide-VDD-range processors using only standard logic gates.  ... 
doi:10.1109/icecs.2016.7841211 dblp:conf/icecsys/BardizbanyanARL16 fatcat:s44zq2wq5ram3bzx6iimsq7v4e

Process variation tolerant pipeline design through a placement-aware multiple voltage island design style

Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
Voltage islands are widely recognized as the state-ofthe-art in MSV design.  ...  Voltage islands are generated by exploiting cell proximity for minimal perturbation of performance pre-optimized placements.  ...  level-shifter free chip-wide high-Vdd designs.  ... 
doi:10.1145/1403375.1403610 fatcat:wvp7ulhlwfdhxbyxmrsv5qnr6a

A 200-MHz 64-b dual-issue CMOS microprocessor

D.W. Dobberpuhl, R.T. Witek, R. Allmon, R. Anglin, D. Bertucci, S. Britton, L. Chao, R.A. Conrad, D.E. Dever, B. Gieseke, S.M.N. Hassoun, G.W. Hoeppner (+11 others)
1992 IEEE Journal of Solid-State Circuits  
The chip is fabricated in a 0.75pm CMOS technology utilizing three levels of metalization and optimized for 3.3-V operation. The die size is 16.8 mm X 13.9 mm and contains 1.68M transistors.  ...  The chip includes separate 8-kilobyte instruction and data caches and a fully pipelined floating-point unit (FPU) that can handle both IEEE and VAX standard floating-point data types.  ...  The interface is fully compatible with virtually any multiprocessor write cache coherence scheme, and can accommodate a wide range of timing parameters.  ... 
doi:10.1109/4.165336 fatcat:zugbyrtgobdzvdiyotfuck5huq

Design issues for dynamic voltage scaling

Thomas D. Burd, Robert W. Brodersen
2000 Proceedings of the 2000 international symposium on Low power electronics and design - ISLPED '00  
A dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability  ...  Processors in portable electronic devices generally have a computational load which has time-varying performance requirements.  ...  One exception to the rule is for circuits in non-critical paths, which can tolerate a widely varying relative delay.  ... 
doi:10.1145/344166.344181 dblp:conf/islped/BurdB00 fatcat:uvbg2n5fq5gcfcnghra4acqsre

Design issues for Dynamic Voltage Scaling

T.D. Burd, R.W. Brodersen
2000 ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)  
A dynamically varying supply voltage has implications on the processor circuit design and design flow, but with some minimal constraints it is straightforward to design a processor with this capability  ...  Processors in portable electronic devices generally have a computational load which has time-varying performance requirements.  ...  One exception to the rule is for circuits in non-critical paths, which can tolerate a widely varying relative delay.  ... 
doi:10.1109/lpe.2000.155245 fatcat:pkirqag5fvc5vczccotljuulx4

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz, Vivek De
2020 Journal of Low Power Electronics and Applications  
We discuss application of NTV design techniques, necessary for reliable operation over a wide supply voltage range—from nominal down to the NTV regime, and for a variety of IPs.  ...  Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches  ...  and promise for wide operational range.  ... 
doi:10.3390/jlpea10020016 fatcat:wuwirnk4ljc7tjllpzc3ng7jei

A DVFS-aware cache bypassing technique for multiple clock domain mobile SoCs

Joonho Kong, Kwangho Lee
2017 IEICE Electronics Express  
Based on the profiled information, our technique adaptively bypasses intermediate levels of caches in the case of abnormal cache hierarchy and applies power-gating to that cache memory for better energy  ...  Multiple clock domains mobile SoCs typically adopt dynamic voltage and frequency scaling (DVFS) for flexible power/energy management.  ...  For example, it is known that Apple A9 mobile processors have 4 MB system-level caches [2] .  ... 
doi:10.1587/elex.14.20170324 fatcat:cmfk2lkav5dlrjvypu36vdgena

Sensor Data Acquisition And De-Noising Using FPGA

Harikrishnan K
2020 International Journal of Scientific and Engineering Research  
As the usage of sensors is increasing, the processor should be capable of handling an enormous amount of data.  ...  The input voltage can range from VSS to VDD. We can tie this pin to VDD.  ...  Supply Voltage Pins (VDD, VSS) VDD is the positive supply voltage input pin. The input supply voltage is relative to VSS and can range from 2.7V to 5.5V.  ... 
doi:10.14299/ijser.2020.08.15 fatcat:hwxnubh3m5hlping3b4mjddtfi

The Tag Filter Architecture: An energy-efficient cache and directory design

Joan J. Valls, Alberto Ros, María E. Gómez, Julio Sahuquillo
2017 Journal of Parallel and Distributed Computing  
For this purpose, the proposed architecture holds the X least significant bits of each tag in a small auxiliary X-bit-wide array.  ...  The proposed approach, called the Tag Filter (TF) Architecture, filters the ways accessed in the target cache set, and just a few ways are searched in the tag and data arrays.  ...  In this work we propose the Tag Filter (TF) Architecture, a technique that can be applied to any set-associative cache in the system, ranging from processor caches that store memory blocks to directory  ... 
doi:10.1016/j.jpdc.2016.04.016 fatcat:6eeu7a3bvbhu5mjh4himb26bjy

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks [article]

Charles Eckert, Xiaowei Wang, Jingcheng Wang, Arun Subramaniyan, Ravi Iyer, Dennis Sylvester, David Blaauw, Reetuparna Das
2018 arXiv   pre-print
This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep Neural Networks.  ...  The Neural Cache architecture is capable of fully executing convolutional, fully connected, and pooling layers in-cache. The proposed architecture also supports quantization in-cache.  ...  ACKNOWLEDGEMENTS We thank members of M-Bits research group for their feedback. This work was supported in part by the NSF CAREER-1652294 award, and Intel gift award.  ... 
arXiv:1805.03718v1 fatcat:d72fse5przg43h5ojhqydsl64i

An Overview of Reconfigurable Hardware in Embedded Systems

Philip Garcia, Katherine Compton, Michael Schulte, Emily Blem, Wenyin Fu
2006 EURASIP Journal on Embedded Systems  
Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems.  ...  Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems.  ...  [9] and an FIR filter operation [8] .  ... 
doi:10.1186/1687-3963-2006-056320 fatcat:lybcy4xldvbvjhhzdci5ws37oy

An Overview of Reconfigurable Hardware in Embedded Systems

Philip Garcia, Katherine Compton, Michael Schulte, Emily Blem, Wenyin Fu
2006 EURASIP Journal on Embedded Systems  
Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems.  ...  Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems.  ...  [9] and an FIR filter operation [8] .  ... 
doi:10.1155/es/2006/56320 fatcat:bxvszbzy7fhgbexlbitlar7bra

A Survey of Emerging Architectural Techniques for Improving Cache Energy Consumption

Washington Bhebhe, Michael Opoku
2016 Communications on Applied Electronics  
A lot of research effort has been put on finding techniques that can improve the energy efficiency of cache architectures.  ...  The search goes on for another ground breaking phenomenon to reduce the ever-increasing disparity between the CPU performance and storage.  ...  The filter data cache is placed between the processor and the L1 cache.  ... 
doi:10.5120/cae2016652443 fatcat:hvi6m63qaredfeg3dzecvjws2e

Performance optimization with scalable reconfigurable computing systems

S. Sangireddy, P. Rajamani, S. Gaddam
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
The scalable coprocessor design for mapping Discrete Cosine Transform (DCT) is implemented with 8 taps resulting in an area of 0.0024ÑÑ ¾ at ¼ ½ technology.  ...  The study also reveals interesting performance patterns for various applications ike CJPEG, MPEG decode/encode, FIR, and IIR, depending on the their characteristics.  ...  For the main processor, we simulated a 4wide out-of-order issue processor with 32 KB L1 I-cache (2-way 1 cycle), 32 KB L1 D-cache (4-way 1 cycle), 256 KB L2 cache (4-way 6 cycle), 100-cycle memory latency  ... 
doi:10.1109/vlsid.2006.133 dblp:conf/vlsid/SangireddyRG06 fatcat:nk7qak5ni5fklnyz3mibnism3y

A highly configurable cache for low energy embedded systems

Chuanjun Zhang, Frank Vahid, Walid Najjar
2005 ACM Transactions on Embedded Computing Systems  
Desktop systems have to accommodate a very wide range of applications and therefore the cache architecture is usually set by the manufacturer as a best compromise given current applications, technology  ...  In this context, a cache architecture that is tuned for that narrow range of applications can have both increased performance as well as lower energy consumption.  ...  The idea of a filter cache is that if most of a program's time is spent in small loops, then most hits would occur in the filter cache, so the more power costly regular cache would be accessed less frequently-thus  ... 
doi:10.1145/1067915.1067921 fatcat:k45tvqwjzvc4pgzympas537r4m
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