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All-Optical Non-Inverted Parity Generator and Checker Based on Semiconductor Optical Amplifiers

2021
*
Applied Sciences
*

The

doi:10.3390/app11041499
fatcat:mcfjtkrtt5dqhb6akox2x4ybnm
*parity*and*check*bits are provided by adjusting the center wavelength of the tunable optical bandpass filter (TOBPF). ... For Pe and Ce (even*parity*bit and even*check*bit) without Clk probe light, ER and OSNR still maintain good performance because of the amplified effect of SOA. ... Experimental parameters*with**logic*gates (P: power*with*dBm unit;*W*: wavelength*with*nm unit; ER: extinction ratio*with*dB unit; OSNR: optical signal to noise ratio*with*dB unit). ...##
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Single-photon-assisted entanglement concentration of a multiphoton system in a partially entangled W state with weak cross-Kerr nonlinearity

2012
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Journal of the Optical Society of America. B, Optical physics
*

We propose a nonlocal entanglement

doi:10.1364/josab.29.001399
fatcat:6e4l6jngnfc6lnweulost2alr4
*concentration*protocol (ECP) for N-photon systems in a partially entangled*W**state*, resorting to some ancillary single photons and the*parity*-*check*measurement based ... standard*W**state*. ...*parity*-*check*detector (PCD) on the polarization*states*of two photons*with*cross-Kerr nonlinearity. ...##
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The application of parity checks to an arithmetic control

1970
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Proceedings of the November 17-19, 1970, fall joint computer conference on - AFIPS '70 (Fall)
*

A circular symbol

doi:10.1145/1478462.1478474
dblp:conf/afips/Disparte70
fatcat:mvh7vgsvqngalp7k2guic4wnhe
*with*only one circle implies a nonrestoring circuit (non-restored*logic*level) whereas a symbol*with*two*concentric*circles implies a restoring circuit. ... Sequential*logic*latch*checking*A*parity*latch is added to a group of control latches to insure proper*parity*. ...##
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A DNA-based parity generator/checker for error detection through data transmission with visual readout and an output-correction function

2017
*
Chemical Science
*

The first DNA-based molecular

doi:10.1039/c6sc04056j
pmid:28553479
pmcid:PMC5424811
fatcat:azt7r3mrhvghjoilq3qtyc5roa
*parity*generator/checker, used for error detection through data transmission*with*fluorescent and visual readouts, has been constructed. ... S10 . † Concatenated*logic*computation There is no doubt that a molecular*logic*system, which could not only execute*parity*generating/*checking*but also perform concatenated*logic*computations, would ... These errors, which have fatal effects on the correct*logic*computation, especially in complicated*logic*circuits, 9, 14, 15 can be*checked*through insertion of a*parity*generator (pG) at the transmitting ...##
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The Planning Spectrum - One, Two, Three, Infinity

2007
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The Journal of Artificial Intelligence Research
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Linear Temporal

doi:10.1613/jair.1909
fatcat:7y6cstro4nb6bhybcnsijqpyk4
*Logic*(LTL) is widely used for defining conditions on the execution paths of dynamic systems. ... In the case of dynamic systems that allow for nondeterministic evolutions, one has to specify, along*with*an LTL formula f, which are the paths that are required to satisfy the formula. ... Theorem 1 The emptiness of a*parity*tree automaton*with*Ò*states*and index can be determined in time Ò Ç´ µ . ...##
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Size-Change Termination and Satisfiability for Linear-Time Temporal Logics
[chapter]

2011
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Lecture Notes in Computer Science
*

In the automata-theoretic framework, finite-

doi:10.1007/978-3-642-24364-6_3
fatcat:qktjgpig2rc4tl6mvcvkhs2pvm
*state*automata are used as a machine model to capture the operational content of temporal*logics*. ...*with*very simple constructions. ...*With*Prop. 4 above it suffices to*check*that LT µ can be translated into alternating*parity*automata that way. ...##
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Higher-order Recursion Schemes and Collapsible Pushdown Automata: Logical Properties

2021
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ACM Transactions on Computational Logic
*

We consider, for both monadic second-order

doi:10.1145/3452917
fatcat:e7pseftknfcxzdwunjwrk6ofkm
*logic*and modal -calculus, three main problems: model-*checking*,*logical*reflection (a.k.a. global model-*checking*, that asks for a finite description of the set ... of elements for which a formula holds), and selection (that asks, if exists, for some finite description of a set of elements for which an MSO formula*with*a second-order free variable holds). ... In a configuration of the form ( , )*with*a*state*of*W*ℓ , A simulates the behaviour of*W*ℓ on at node in*state*by a sequence of -transitions. ...##
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Efficient fault-tolerant quantum computing

1999
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Nature
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Fault tolerant quantum computing methods which work

doi:10.1038/20127
fatcat:hkmej6w6rjbmdiq7li6vfsuymq
*with*efficient quantum error correcting codes are discussed. ... It is found that, under the standard noise model of ubiquitous stochastic, uncorrelated errors, a quantum computer need be only an order of magnitude larger than the*logical*machine contained within it ...*check*matrix C ⊥ 0 , so uD satisfies the*parity**check*x ∈ C 0 . ...##
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Topological order in an exactly solvable 3D spin model

2011
*
Annals of Physics
*

We describe a complete set of

doi:10.1016/j.aop.2010.11.002
fatcat:373ykpbqtbalhhnvnn6iy7iimu
*logical*operators acting on the encoded qubits in terms of closed strings and closed membranes. ... This is an exactly solvable spin model*with*six-qubit nearest neighbor interactions on an FCC lattice whose ground space exhibits topological quantum order. ... BMT and SB would like to thank Dave Bacon for first introducing this spin model to them and they acknowledge insightful discussions concerning properties of the model*with*Panos Aliferis, Dave Bacon and ...##
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Area efficient architectures for information integrity in cache memories

1999
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SIGARCH Computer Architecture News
*

We evaluate the effectiveness of the proposed schemes using a trace-driven simulation combined

doi:10.1145/307338.301000
fatcat:pueuy5wv5baotopvnlp3xyvg6u
*with*software error injection using four different fault manifestation models. ... Conventional architectures for enhancing cache reliability using*check*codes make it difficult to trade between the level of data integrity and the chip area requirement. ... Figure 2 shows the*logical*organization of a 16KB directmapped data cache or D-cache (left half) protected by a*parity*cache of 16 entries (right half) in conjunction*with*an ECC unit. ...##
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Higher-Order Recursion Schemes and Collapsible Pushdown Automata: Logical Properties
[article]

2021
*
arXiv
*
pre-print

We consider, for both monadic second-order

arXiv:2010.06366v2
fatcat:htqiqtp3rfaxxattbycq4hlhsq
*logic*and modal mu-calculus, three main problems: model-*checking*,*logical*reflection (aka global model-*checking*, that asks for a finite description of the set ... of elements for which a formula holds) and selection (that asks, if exists, for some finite description of a set of elements for which an MSO formula*with*a second-order free variable holds). ... In a configuration of the form ( , )*with*a*state*of*W*ℓ , A simulates the behaviour of*W*ℓ on at node in*state*by a sequence of -transitions. ...##
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A landscape with games in the background

2004
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Proceedings of the 19th Annual IEEE Symposium on Logic in Computer Science, 2004.
*

Several extensions of the standard model of finite games

doi:10.1109/lics.2004.1319630
dblp:conf/lics/Walukiewicz04
fatcat:g32dgr7wfrg3zljielb4auyole
*with*regular winning conditions are discussed. One direction is that of considering non-regular winning conditions. ... In what concerns verification, we will mostly*concentrate*on the model-*checking*problem, that is the problem of verifying if a given formula holds in a given*state*of a given model. ... From*parity*games to model*checking*The match between*parity*games and model-*checking*works both ways. ...##
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Error- and flow-control protocols for terabit optical networks

2000
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Optoelectronic Interconnects VII; Photonics Packaging and Integration II
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Conventional error control protocols are infeasible

doi:10.1117/12.384387
fatcat:wftluuuuzff5hewalqjf24of54
*with*dense bit parallel optical systems based on image guides since they require excessive amounts of hardware. ... The long packet format consists of 720 bytes,*with*a 16 byte header, a 516 bytes of payload, 8 bytes of trailer and 186 bytes of*parity**check*. ... The*parity**check*detects this situation by observing*parity*errors in exactly 2 rows and 2 columns. ...##
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Low-overhead fault-tolerant quantum computing using long-range connectivity
[article]

2021
*
arXiv
*
pre-print

We present a scheme for low-overhead fault-tolerant quantum computation based on quantum low-density

arXiv:2110.10794v1
fatcat:rozeh7ouirhddis4cmw5hbcxki
*parity*-*check*(LDPC) codes, where the capability of performing long-range entangling interactions allows ... a large number of*logical*qubits to be encoded*with*a modest number of physical qubits. ... The proof of more general*logical**parity*measurements can be obtained*with*the methods we develop here*with*the most simple case. LetZ be a Z*logical*operator contained entirely in C. ...##
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A simple, label-free, electrochemical DNA parity generator/checker for error detection during data transmission based on "aptamer-nanoclaw"-modulated protein steric hindrance

2018
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Chemical Science
*

The first electrochemical DNA

doi:10.1039/c8sc02482k
pmid:30210773
pmcid:PMC6124900
fatcat:33rh5ucavrcobhj7vwt4zhtege
*parity*generator/checker system for error detection during data transmission was constructed based on "aptamer-nanoclaw"-modulated protein steric hindrance. ... Aer washing*with*Tris-HCl*W*-buffer, the MCH/S/Au electrode was obtained. ... Compared*with*simple*logic*gates, cascade*logic*circuits could perform more complicated*logic*computation. ...
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