Filters








1,563 Hits in 6.3 sec

Automated synthesis for asynchronous FPGAs

Song Peng, David Fang, John Teifel, Rajit Manohar
2005 Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays - FPGA '05  
We present an automatic logic synthesis method targeted for highperformance asynchronous FPGA (AFPGA) architectures.  ...  For a wide variety of benchmarks, our automatic synthesis method not only yields comparable logic densities and performance to those achieved by hand placement, but also attains a throughput close to the  ...  or based on synchronous designs.  ... 
doi:10.1145/1046192.1046214 dblp:conf/fpga/PengFTM05 fatcat:siz6czvw2nfqzpvaxbvqs63sd4

Learning hardware using multiple-valued logic - Part 1: introduction and approach

M. Perkowski, D. Foote, Qihong Chen, A. Al-Rabadi, L. Jozwiak
2002 IEEE Micro  
However, in test generation 1 and combinatorial optimization areas, reconfigurable, field-programmable-gate-array (FPGA)-based processors can solve some nondeterministic polynomial time (NP)-hard problems  ...  Machine learning has become a general paradigm for software system design, unifying all these previously disconnected areas. With the  ...  Logic-based learning Logic synthesis researchers and engineers in design automation for digital circuits develop efficient logic network synthesis algorithms.  ... 
doi:10.1109/mm.2002.1013303 fatcat:fjeo52iks5hafg5gcuz53h7sxy

Asynchronous microprocessors: From high level model to FPGA implementation

L. Lloyd, K. Heron, A.M. Koelmans, A.V. Yakovlev
1999 Journal of systems architecture  
In order to determine the applicability of both programmable software tools and programmable hardware for asynchronous logic applications an implementation, employing FPGA devices, of the instruction decode  ...  A number of the asynchronous speci c areas of the ADLX have been synthesized using Petrify, a Petri Net tool designed for the manipulation of concurrent speci cations of asynchronous control circuits.  ...  Acknowledgements We wish to thank Vince Bilton and the members of the Computing Service Network Group for providing the laboratory facilities that enabled the pursuance of this project.  ... 
doi:10.1016/s1383-7621(98)00047-2 fatcat:m6bt3go5hnb5rhek3q7zsrfibq

RASP: A General Logic Synthesis System for SRAM-Based FPGAs

J. Cong, J. Peck, Yuzheng Ding
1996 Fourth International ACM Symposium on Field-Programmable Gate Arrays  
In this paper, we present a general synthesis system for SRAM-based FPGAs named RASP.  ...  As a result, RASP can produce highly optimized designs for various SRAM-based FPGA architectures, and can be quickly adapted for new SRAM-based FPGA architectures.  ...  In order to fulfill these two needs, RASP was developed as a general synthesis system for SRAM-based FPGAs.  ... 
doi:10.1109/fpga.1996.242541 fatcat:yu53ptgpwbf6nnoqeaigokrawm

RASP

Jason Cong, John Peck, Yuzheng Ding
1996 Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays - FPGA '96  
In this paper, we present a general synthesis system for SRAM-based FPGAs named RASP.  ...  As a result, RASP can produce highly optimized designs for various SRAM-based FPGA architectures, and can be quickly adapted for new SRAM-based FPGA architectures.  ...  In order to fulfill these two needs, RASP was developed as a general synthesis system for SRAM-based FPGAs.  ... 
doi:10.1145/228370.228390 dblp:conf/fpga/CongPD96 fatcat:ba4zachfijghtpxprpom377as4

Logic synthesis for field-programmable gate arrays

Ting-Ting Hwang, R.M. Owens, M.J. Irwin, Kuo Hua Wang
1994 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods.  ...  Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more  ...  We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods.  ... 
doi:10.1109/43.317471 fatcat:bqpd3ulpnrdphmjvvmcm7uzxz4

FPGA Latency Optimization Using System-level Transformations and DFG Restructuring

Daniel Gomez-Prado, Maciej Ciesielski, Russell Tessier
2013 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013  
This paper describes a system-level approach to improve the latency of FPGA designs by performing optimization of the design specification on a functional level prior to highlevel synthesis.  ...  Our approach engages several passes of a traditional high-level synthesis (HLS) process in a simulated annealing-based loop to make efficient cost tradeoffs.  ...  TED-based Decomposition System (TDS) A guided TED-based decomposition provides a means for effective design space exploration. This idea is illustrated in Fig. 2 .  ... 
doi:10.7873/date.2013.316 dblp:conf/date/Gomez-PradoCT13 fatcat:orwlzfj3rvb3zpdnffrudsadla

Low Power Area Optimum Configurable 160 to 2560 Subcarrier Orthogonal Frequency Division Multiplexing Modulator-Demodulator Architecture based on Systolic Array and Distributive Arithmetic Look-Up Table

2021 Informacije midem  
Distributive Arithmetic (MDA) algorithm is designed for low power underwater MODEM applications.  ...  The OSA structure is designed with optimum placement of Processing Elements (PE) and the MDA structure is designed to compute two filter outputs per module with Look-Up Table ( LUT) of depth 8.  ...  In this paper, pipelined and optimized filter structures are designed for computing both DTCWT and inverse DTCWT based on OSA logic for OFDM.  ... 
doi:10.33180/infmidem2021.204 fatcat:t4xxtiizkrdl3pxwdu3npdy6zi

The Case Study of Block Turbo Decoders on a Framework for Portable Synthesis on FPGA

C. Dezan, C. Jego, B. Pottier, C. Gouyen, L. Lagadec
2006 Proceedings of the 39th Annual Hawaii International Conference on System Sciences (HICSS'06)  
Madeo is an open framework for designing physical FPGA architectures and their applications.  ...  On the basis of an abstract model for reconfigurable circuits, Madeo provides the necessary tools (logic synthesis and physical tool) to program them.  ...  Thanks also to Caaliph Andrianisaina and Herve Le Guen for their technical participations to this project.  ... 
doi:10.1109/hicss.2006.453 dblp:conf/hicss/DezanJPGL06 fatcat:ibw6deu43zbxndrcyakbn7penm

Reconfigurable Logic Controller—Direct FPGA Synthesis Approach

Adam Milik, Marcin Kubica, Dariusz Kania
2021 Applied Sciences  
Programmable logic controllers are commonly used in automation systems. Continuously growing demands result in the growth of control program complexity.  ...  The intermediate form is optimized using flow graph representation and BDDs for analyzing logic dependencies.  ...  Presented methods lack the advanced logic synthesis procedures for the efficient utilization of logic resources of FPGA devices.  ... 
doi:10.3390/app11188515 fatcat:k4y2nqr53zfqlljfmvkkdgv3oa

A General Approach to Boolean Function Decomposition and its Application in FPGABased Synthesis

Tadeusz Łuba, Henry Selvaraj
1995 VLSI design (Print)  
An effective logic synthesis procedure based on parallel and serial decomposition of a Boolean function is presented in this paper.  ...  The decomposition, carried out as the very first step of the .synthesis process, is based on an original representation of the function by a set of r-partitions over the set of minterms.  ...  This has been a primary reason for recent interest in FPGA based logic synthesis.  ... 
doi:10.1155/1995/67208 fatcat:xb6j3kvi75gklea7inqpc4ehea

Synthesis of Macro Petri Nets into FPGA with Distributed Memories

Arkadiusz Bukowiec, Marian Adamski
2012 International Journal of Electronics and Telecommunications  
In this paper a new method of Petri net array-based synthesis is proposed. The method is based on decomposition of colored interpreted macro Petri net into state machine subnets.  ...  It leads to realization of a logic circuit in a two-level concurrent structure, where the combinational circuit of the first level is responsible for firing transitions, and the second level memories are  ...  In this case Petri nets (PNs) [6] , [7] are one of the most adequate methods for formal design of application specific logic controllers [1] .  ... 
doi:10.2478/v10177-012-0055-x fatcat:oxclt474ovduhkzz7bktatoewe

Module generation of complex macros for logic-emulation applications

Wen-Jong Fang, Allen C.-H. Wu, Duan-Ping Chen
1997 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays - FPGA '97  
Furthermore, the module generator can e ectively generate a multiple-FPGA macro for large macros which can not t in a single FPGA chip.  ...  Logic emulation is a technique that uses dynamically reprogrammable systems for prototyping and design veri cation.  ...  Acknowledgments This work was supported in part by the National Science Council of R.O.C. under Grant NSC 86-2221-E-007-047 and by a grant from the Quickturn Design Systems Inc.  ... 
doi:10.1145/258305.258314 dblp:conf/fpga/FangWC97 fatcat:47bx26b63vguvmrb2apqhqe6rq

A domain specific reconfigurable Viterbi fabric for system-on-chip applications

Cheng Zhan, Tughrul Arslan, Sami Khawam, Iain Lindsay
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC.  ...  The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend.  ...  The synthesis and mapping tools for FPGA device is ISE V6.2i of Xilinx, Inc.  ... 
doi:10.1145/1120725.1121069 dblp:conf/aspdac/ZhanAKL05 fatcat:ujjbjci55ve7vapn6xluq4xdvm

A high performance synthesisable unsymmetrical reconfigurable fabric for heterogeneous finite state machines

Zhenyu Liu, Tughrul Arslan, Sami Khawam, Iain Lindsay
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
A reconfigurable Finite State Machine (FSM) is constantly required for the purpose of control in any reconfigurable SoC.  ...  The use of synthesizable reconfigurable cores in system on chip (SoC) designs is increasingly becoming a trend.  ...  The synthesis and mapping tools for FPGA device is ISE V6.2i of Xilinx, Inc.  ... 
doi:10.1145/1120725.1120983 dblp:conf/aspdac/LiuAKL05 fatcat:wg2sllqhtre6lbjun72ylk3lw4
« Previous Showing results 1 — 15 out of 1,563 results