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LogTM-SE: Decoupling Hardware Transactional Memory from Caches

Luke Yen, Jayaram Bobba, Michael R. Marty, Kevin E. Moore, Haris Volos, Mark D. Hill, Michael M. Swift, David A. Wood
2007 2007 IEEE 13th International Symposium on High Performance Computer Architecture  
This paper proposes a hardware transactional memory (HTM) system called LogTM Signature Edition (LogTM-SE).  ...  First, signatures and logs can be implemented without changes to highly-optimized cache arrays because LogTM-SE never moves cached data, changes a block's cache state, or flash clears bits in the cache  ...  Acknowledgements This work is supported in part by the National Science Foundation (NSF), with grants CCF-0085949, CCR-0105721, EIA/CNS-0205286, CCR-0324878, as well as donations from Intel and Sun Microsystems  ... 
doi:10.1109/hpca.2007.346204 dblp:conf/hpca/YenBMMVHSW07 fatcat:tvfgjofjerek3ju3wqa4mwotuq

FASTM: A Log-based Hardware Transactional Memory with Fast Abort Recovery

Marc Lupon, Grigorios Magklis, Antonio Gonzalez
2009 2009 18th International Conference on Parallel Architectures and Compilation Techniques  
Version management, one of the key design dimensions of Hardware Transactional Memory (HTM) systems, defines where and how transactional modifications are stored.  ...  Simulation results show that FASTM achieves a speed-up of 43% compared to LogTM-SE, improving the scalability of applications with coarse-grain transactions and obtaining similar performance to an ideal  ...  LogTM-SE [14] decouples transactional state from caches, replacing the Read-Write bits of LogTM with signatures [26] .  ... 
doi:10.1109/pact.2009.19 dblp:conf/IEEEpact/LuponMG09 fatcat:gzg62rdxifh65nrc6blmu4fu7y

Directory-Based Conflict Detection in Hardware Transactional Memory [chapter]

Rubén Titos, Manuel E. Acacio, José M. García
2008 Lecture Notes in Computer Science  
One of the key design points of any hardware transactional memory (HTM) system is the conflict detection mechanism, and its efficient implementation becomes critical when conflicts are not a rare event  ...  Simulation results show that our approach obtains reductions in execution time between 25 and 55% for transactional benchmarks with a high number of conflicts, with an average improvement over LogTM-SE  ...  Rubén Titos is supported by a research grant from the Spanish MEC under the FPU National Plan (AP2006-04152). The authors would like to thank the anonymous reviewers for their helpful insights.  ... 
doi:10.1007/978-3-540-89894-8_47 fatcat:yjudwtx7afbbxbwsf7nf5q4xgu

Soft-error mitigation by means of decoupled transactional memory threads

Daniel Sánchez, Juan M. Cebrián, José M. García, Juan L. Aragón
2014 Distributed computing  
Based on a Hardware Transactional Memory architecture, LBRA executes redundant threads which communicate through a pairshared virtual memory log allocated in cache.  ...  However, these proposals are usually implemented over non-realistic environments including the use of shared-buses among processors or modifying highly optimized hardware designs such as caches.  ...  The semantic and execution of a p-XACT differ from a regular transaction in LogTM-SE.  ... 
doi:10.1007/s00446-014-0215-6 fatcat:vdvalpdcwrbt3ofopss4nncl4q

Characterizing Energy Consumption in Hardware Transactional Memory Systems

Epifanio Gaona-Ramirez, Ruben Titos-Gil, Juan Fernandez, Manuel E. Acacio
2010 2010 22nd International Symposium on Computer Architecture and High Performance Computing  
In this way, future many-core CMP architectures may need to provide hardware support for transactional memory.  ...  More specifically, we compare the LogTM-SE Eager-Eager system and a version of the Scalable TCC Lazy-Lazy system that enables parallel commits.  ...  Epifanio Gaona Ramírez is supported by fellowship 09503/FPI/08 from Fundación Séneca, Agencia Regional de Ciencia y Tecnología de la Región de Murcia (II PCTRM).  ... 
doi:10.1109/sbac-pad.2010.11 dblp:conf/sbac-pad/Gaona-RamirezTFA10 fatcat:ke6qxidq3zcnjfhuikgjfah34a

A log-based redundant architecture for reliable parallel computation

Daniel Sanchez, Juan L. Aragon, Jose M. Garcia
2010 2010 International Conference on High Performance Computing  
To this end, we propose LBRA based on a Hardware Transactional Memory (HTM) architecture in which two redundant threads successfully detects and recovers from transient faults, assuring a consistent view  ...  However, these proposals are usually implemented over non-realistic environments including the use of shared-buses among processors or modifying highly optimized hardware designs such as caches.  ...  Reliable Computation by means of Transactional Memory Our approach is built upon the top of a LogTM-SE [22] system, a hardware implementation of Transactional Memory.  ... 
doi:10.1109/hipc.2010.5713183 dblp:conf/hipc/SanchezAG10 fatcat:kpnvrt4mubghdnjz236szv36vu

Flexible Decoupled Transactional Memory Support

Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2008 SIGARCH Computer Architecture News  
We propose that the requisite hardware mechanisms be decoupled from one another.  ...  This allows us to virtualize these structures, extending transactions through context switches and paging. As in LogTM-SE, summary signatures capture the read and write sets of swapped-  ...  However, because we flush speculative state from the local cache when descheduling a transaction, unlike LogTM-SE, the summary signature is not on the path of every L1 access, but rather, is checked only  ... 
doi:10.1145/1394608.1382134 fatcat:hnt46ouzcba3hhlrjeywq6jbrq

Version management alternatives for hardware transactional memory

Marc Lupon, Grigorios Magklis, Antonio González
2008 Proceedings of the 9th workshop on MEmory performance DEaling with Applications, systems and architecture - MEDEA '08  
Hardware Transactional Memory (HTM) implements these mechanisms in silicon to obtain better results than fine-grain locking solutions.  ...  Hardware  ...  LogTM-SE [21] decouples transactional state from caches, replacing Read-Write bits with signatures. A signature is a compact representation of a set of memory addresses.  ... 
doi:10.1145/1509084.1509094 fatcat:t3qtssordnh47i7db7yqusyssa

Flexible Decoupled Transactional Memory Support

Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2008 2008 International Symposium on Computer Architecture  
We propose that the requisite hardware mechanisms be decoupled from one another.  ...  This allows us to virtualize these structures, extending transactions through context switches and paging. As in LogTM-SE, summary signatures capture the read and write sets of swapped-  ...  However, because we flush speculative state from the local cache when descheduling a transaction, unlike LogTM-SE, the summary signature is not on the path of every L1 access, but rather, is checked only  ... 
doi:10.1109/isca.2008.17 dblp:conf/isca/ShriramanDS08 fatcat:kwyihhdwpbentfbnd4anoqzaei

TokenTM: Efficient Execution of Large Transactions with Hardware Transactional Memory

Jayaram Bobba, Neelam Goyal, Mark D. Hill, Michael M. Swift, David A. Wood
2008 2008 International Symposium on Computer Architecture  
Current hardware transactional memory systems seek to simplify parallel programming, but assume that large transactions are rare, so it is acceptable to penalize their performance or concurrency.  ...  memory.  ...  TokenTM decouples a block's transactional memory state from its cache coherence state.  ... 
doi:10.1109/isca.2008.24 dblp:conf/isca/BobbaGHSW08 fatcat:f2cpuzdfabdixap4n6lreva7pa

Implementation tradeoffs in the design of flexible transactional memory support

Arrvindh Shriraman, Sandhya Dwarkadas, Michael L. Scott
2010 Journal of Parallel and Distributed Computing  
Finally, we compare the use of an aggressive hardware controller (as used in the base FlexTM design) to manage and to access any speculative transaction state overflowed from the cache, to a hardware-software  ...  hardware to manage transactional state and to track conflicts.  ...  For (2) we adapt a solution first proposed in LogTM-SE [46] .  ... 
doi:10.1016/j.jpdc.2010.03.006 fatcat:6im5tb4ihfblhaz3t5ibyjsu3y

LiteTM: Reducing transactional state overhead

Syed Ali Raza Jafri, Mithuna Thottethodi, T N Vijaykumar
2010 HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture  
Hardware implementations of transactional memory (HTMs) have made significant progress in providing support for features such as long transactions that spill out of the cache, and context switches, page  ...  Transactional memory (TM) has been proposed to address some of the programmability issues of chip multiprocessors.  ...  LogTM-SE TokenTM vs.  ... 
doi:10.1109/hpca.2010.5416653 dblp:conf/hpca/JafriTV10 fatcat:cmb5gc64pncarnpkn2vfyibs2y

Using hardware transactional memory for data race detection

Shantanu Gupta, Florin Sultan, Srihari Cadambi, Franjo Ivancic, Martin Rotteler
2009 2009 IEEE International Symposium on Parallel & Distributed Processing  
In particular, we show how emerging hardware support for transactional memory can be leveraged to aid data race detection.  ...  We propose the concept of lightweight debug transactions that exploit the conflict detection mechanisms of transactional memory systems to perform data race detection.  ...  LogTM-SE supports transaction virtualization by decoupling transactional state from caches and enabling software to manipulate it.  ... 
doi:10.1109/ipdps.2009.5161006 dblp:conf/ipps/GuptaSCIR09 fatcat:erm6mlqi4vhlbh3r4qil4x3mjy

Characterization of Conflicts in Log-Based Transactional Memory (LogTM)

J. Ruben Titos Gil, Manuel E. Acacio Sanchez, Jose M. Garcia Carrasco
2008 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)  
Hardware transactional memory (HTM) systems implement the necessary mechanisms to provide transactional semantics efficiently.  ...  Transactional memory has been proposed as an abstraction capable of ameliorating the challenges of traditional lock-based parallel programming.  ...  Rubén Titos is supported by a research grant from the Spanish MEC under the FPU national plan (AP2006-04152).  ... 
doi:10.1109/pdp.2008.63 dblp:conf/pdp/GilSC08 fatcat:ikzrtbhssnb5dphbqgawcrljgy

Mapping Out a Path from Hardware Transactional Memory to Speculative Multithreading

Leo Porter, Bumyong Choi, Dean M. Tullsen
2009 2009 18th International Conference on Parallel Architectures and Compilation Techniques  
This research demonstrates that coming support for hardware transactional memory can be leveraged to significantly reduce the cost of implementing true speculative multithreading.  ...  The result is a unified memory architecture capable of effective support for transactional parallel workloads and efficient speculative multithreading.  ...  This design has the same conflict detection semantics as those in LogTM-SE [9] and TokenTM [3] . It is also likely to be similar to the hardware support in SUN's Rock Processor [14] , [33] .  ... 
doi:10.1109/pact.2009.37 dblp:conf/IEEEpact/PorterCT09 fatcat:4ldki34k4ncyjc4sfukl2gqbsy
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