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Register integration

Amir Roth, Gurindar S. Sohi
2000 Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture - MICRO 33  
Using an auxiliary table, this circuit searches the physical register file for the physical register belonging to the corresponding squashed instance of the instruction.  ...  Integration reduces contention for queuing and execution resources, collapses dependent chains of instructions and accelerates the resolution of branches.  ...  School and an Intel Ph.D Fellowship.  ... 
doi:10.1145/360128.360151 fatcat:bfhabc7h6jg6zk2nh434yfdpnq

Squash Reuse via a Simplified Implementation of Register Integration

Amir Roth, Gurindar S. Sohi
2001 Journal of Instruction-Level Parallelism  
Register integration (or simply integration) is a mechanism for the direct reuse of previously computed results. Integration uses data-dependence relationships to test for and establish reusability.  ...  As the processor re-traces portions of the squashed path, an auxiliary table is used to search the physical register file for the registers belonging to the corresponding squashed instances of re-traced  ...  of Wisconsin Graduate School and an Intel Ph.D Fellowship.  ... 
dblp:journals/jilp/RothS01 fatcat:nbqpyisxc5ehhiabk2tjey4j7q

On the Effectiveness of Code-Reuse-Based Android Application Obfuscation [chapter]

Xiaoxiao Tang, Yu Liang, Xinjie Ma, Yan Lin, Debin Gao
2017 Lecture Notes in Computer Science  
Moreover, we extend code-reuse-based obfuscation to the Android platform by proposing an obfuscation mechanism for both Java and native code.  ...  Furthermore, we implement a semi-automatic tool named AndroidCubo and show that it protects both Java and native code with comparable security to those obfuscated with Java reflection at a small runtime  ...  In this sequence, gadgets 1-3 are used to load the first operand to register R9. Gadgets 4-6 are used to load the second operand to register R3.  ... 
doi:10.1007/978-3-319-53177-9_18 fatcat:g5gm5xy7nnbvhl3v4net7r4wly

Register Pointer Architecture for Efficient Embedded Processors

JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
2007 2007 Design, Automation & Test in Europe Conference & Exhibition  
Additional register file capacity allows many loads and stores, such as those introduced by spill code, to be eliminated, which improves performance and reduces energy consumption.  ...  Indirection allows a larger register file to be used without increasing the length of instruction words.  ...  Existing arithmetic and load/store instructions can use a register pointer (RP) in any register operand position to access the contents of the DRF.  ... 
doi:10.1109/date.2007.364659 dblp:conf/date/ParkPBBKD07 fatcat:4gmk2jdkh5artbqhvuzgbbz7m4

Automatic Safe Data Reuse Detection for the WCET Analysis of Systems with Data Caches

Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Victor Vinals
2020 IEEE Access  
As a proof of concept we analyze the TACLeBench benchmark suite, showing that most loads/stores present data reuse, and how compiler optimizations affect it.  ...  Caches exploit the inherent reuse properties of programs, temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers  ...  In Table 1 , for each benchmark and optimization level, columns under ''Dominant loads/stores with exploitable reuse'' show the number of load/store instructions that bring content with exploitable reuse  ... 
doi:10.1109/access.2020.3032145 fatcat:dbn5d7tjx5cololsoxg5r4bepe

Speculative execution for hiding memory latency

Alex Pajuelo, Antonio González, Mateo Valero
2004 Proceedings of the 2004 workshop on MEmory performance DEaling with Applications , systems and architecture - MEDEA '04  
When these dynamic instructions are later fetched, they use the previously precomputed data and directly go to the commit stage without executing.  ...  L2 misses are one of the main causes for stalling the activity in current and future microprocessors.  ...  Intel Corporation and the European Network of Excellence on High-Performance Embedded Architecture and Compilation (HiPEAC).  ... 
doi:10.1145/1152922.1101877 fatcat:fmhn7bnkonfrpnzga4p3ejchva

Speculative execution for hiding memory latency

Alex Pajuelo, Antonio González, Mateo Valero
2005 SIGARCH Computer Architecture News  
When these dynamic instructions are later fetched, they use the previously precomputed data and directly go to the commit stage without executing.  ...  L2 misses are one of the main causes for stalling the activity in current and future microprocessors.  ...  Since replicas are created and executed out of the critical path, and the precomputed values will not be used as soon as created, a hierarchical register file has been implemented to store the speculative  ... 
doi:10.1145/1101868.1101877 fatcat:woda6imefnf6jfr2lmkbwa7f5e

BOLT: Energy-efficient Out-of-Order Latency-Tolerant execution

Andrew Hilton, Amir Roth
2010 HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture  
An LT core increases ILP without physically scaling the issue queue and register file and increases MLP without additional software threads that can reduce cache performance.  ...  We introduce a microarchitecture called BOLT (Better Out-of-Order Latency-Tolerance) that implements LT as an alternative use of SMT (Simultaneous Multi-Threading).  ...  and register file.  ... 
doi:10.1109/hpca.2010.5416634 dblp:conf/hpca/HiltonR10 fatcat:eegugksit5alzh2wx5tqg3dqcy

Implementation of ETL Process using Pig and Hadoop

2020 International journal of recent technology and engineering  
In this paper we demonstrate the ETL process using Pig in Hadoop. Here we demonstrate how the files in HDFS are extracted, transformed and loaded back to HDFS using Pig.  ...  of certain rules and loading stores back the data to the destination repository where it has to finally reside.  ...  We perform extraction, transformation and loading of files from and store it back into the HDFS using Pig. The functionalities in Pig Latin is coded using Python UDFs to perform transformations.  ... 
doi:10.35940/ijrte.e4901.018520 fatcat:v7gfeoqs6zbxhm6ntxty4zufxq

Heuristic tradeoffs between latency and energy consumption in register assignment

R. Anand, M. Jacome, G. de Veciana
2000 Proceedings of the eighth international workshop on Hardware/software codesign - CODES '00  
One of the challenging tasks in code generation for embedded systems is register allocation and assignment, wherein one decides on the placement and lifetimes of variables in registers.  ...  When there are more live variables than registers, some variables need to be spilled to memory and restored later.  ...  Indeed, in this scenario, there are few opportunities to keep local data objects and primary inputs in the register file so that they may be reused later and thus the same number of load/stores are obtained  ... 
doi:10.1145/334012.334034 dblp:conf/codes/AnandJV00 fatcat:xiaow5af2begrommsejdowrp3u

AVRAND: A Software-Based Defense Against Code Reuse Attacks for AVR Embedded Devices [chapter]

Sergio Pastrana, Juan Tapiador, Guillermo Suarez-Tangil, Pedro Peris-López
2016 Lecture Notes in Computer Science  
ASLR and Control Flow Integrity are two mechanisms commonly used to deter automated attacks based on code reuse.  ...  In this work, we present a code reuse attack against embedded AVR devices that shows how an adversary can execute arbitrary code reused from the firmware and other external libraries.  ...  This work was supported by the MINECO Grant TIN2013-46469-R (SPINY), by the CAM Grant S2013/ICE-3095 (CIBERDINE) and by the UK EPSRC grant EP/L022710/1.  ... 
doi:10.1007/978-3-319-40667-1_4 fatcat:gdpapyvstnasdno5ta42rhbiuy

An SSL Back-End Forwarding Scheme in Cluster-Based Web Servers

Jin-Ha Kim, Gyu Sang Choi, Chita R. Das
2007 IEEE Transactions on Parallel and Distributed Systems  
The application server handles dynamic and sensitive Web contents that need protection from eavesdropping, tampering and forgery.  ...  State-of-the-art cluster-based data centers consisting of three tiers (Web server, application server and database server) are being used to host complex Web services such as e-commerce applications.  ...  The administrator will do components and the operating procedures of the the encryption of the text file and store into the servers system. which we are assigned in IP representation module.  ... 
doi:10.1109/tpds.2007.1062 fatcat:xgk6dl3rojbpbnywtpierzgrzm

On the Effectiveness of Flow Aggregation in Improving Instruction Reuse in Network Processing Applications

G. Surendra, S. Banerjee, S. K. Nandy
2003 International journal of parallel programming  
and (3) What is the effect of reuse on microarchitectural features such as resource contention and memory accesses?  ...  In this paper we examine instruction reuse of integer ALU and load instructions in network processing applications and attempt to answer the following questions: (1) How much of instruction repetition  ...  In case of load instructions, reuse (outcome of load being reused) reduces port contention, number of memory accesses (11) and bus transitions.  ... 
doi:10.1023/b:ijpp.0000004511.82411.d4 fatcat:pmrhthxutzdlhkmtr5drbywuvq

Oxymoron: Making Fine-Grained Memory Randomization Practical by Allowing Code Sharing

Michael Backes, Stefan Nürnberger
2014 USENIX Security Symposium  
Our theoretical and practical evaluations show that Oxymoron is the first solution to be secure against just-in-time code reuse attacks and demonstrate that fine-grained memory randomization is feasible  ...  The latest effective defense against code reuse attacks is fine-grained, per-process memory randomization.  ...  In PALACE code this register loading looks like this: mov %fs:$0x4, %eax. This copies an address stored as an entry in the RaTTle to the register %eax.  ... 
dblp:conf/uss/BackesN14 fatcat:b5fa4i4b6vfqzd6hv7liu4vvni

Instruction set extension for high throughput disparity estimation in stereo image processing

Christian Banz, Carsten Dolar, Fabian Cholewa, Holger Blume
2011 ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors  
This paper presents the implementation and evaluation of an application-specific instruction set for a customizable RISC-processor for very high throughput stereo image processing.  ...  This implies a more data-greedy algorithm implementation which requires higher bandwidth load/store operations and increased data reuse. • Maximize data reuse.  ...  A VR_RL128 (ring load) instruction first shifts left the register content by 128 bits and then loads a 128-bit word from memory into to the lower part.  ... 
doi:10.1109/asap.2011.6043265 dblp:conf/asap/BanzDCB11 fatcat:hlhshzsnh5h7noha2bjhypm3dq
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