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Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture

D.A.B. Miller, H.M. Ozaktas
1997 Journal of Parallel and Distributed Computing  
interconnection to the total cross-sectional dimension p A A A of the interconnect wiring-the "aspect ratio" of the interconnection.  ...  We show that there is a limit to the total number of bits per second, B, of information that can flow in a simple digital electrical interconnection that is set only by the ratio of the length l of the  ...  This aspect ratio limit to electrical bit-rate capacity is relatively universal.  ... 
doi:10.1006/jpdc.1996.1285 fatcat:tyy5cjh3src3pisjbasj4bhetm

2D parallel optical interconnects between CMOS ICs

O. Rits, M. De Wilde, G. Roelkens, R. Bockstaele, Richard Annen, Martin Bossard, Francois Marion, R. Baets, Louay A. Eldada, El-Hang Lee
2006 Optoelectronic Integrated Circuits VIII  
Due to different frequency-dependent sources of signal degradation, the performance of these electrical interconnects lags behind the IC performance.  ...  From this we then consider the implications on the introduction of optical interconnects and we argue why integration is of key importance for the successful introduction of optical interconnects at this  ...  The authors thank Avalon Photonics for the InGaAs-based VCSELs, Albis Optoelectronics AG for the InP-based photodiodes, and the TFCG department of Ghent University for the assembly of the system demonstrator  ... 
doi:10.1117/12.652108 fatcat:6cqxl6brh5fxjkvm7yrbp4rfkm

Silicon Microphotonics [chapter]

L. C. Kimerling
2003 Interconnect Technology and Design for Gigascale Integration  
The key frontier is the large scale integration and manufacturing of photonic components to enable the distribution of high bit rate optical streams to the individual information appliance.  ...  Each network node that requires transduction from photonics to electronics limits the performance and affordability of the network.  ...  Acknowledgements I am indebted to the students and colleagues listed in the references who inspired and implemented this work. Professor Hermann Haus and Dr.  ... 
doi:10.1007/978-1-4615-0461-0_10 fatcat:uetq2ljrzfeqfcbk34blml5y3u

Silicon microphotonics

Lionel C Kimerling
2000 Applied Surface Science  
The key frontier is the large scale integration and manufacturing of photonic components to enable the distribution of high bit rate optical streams to the individual information appliance.  ...  Each network node that requires transduction from photonics to electronics limits the performance and affordability of the network.  ...  Acknowledgements I am indebted to the students and colleagues listed in the references who inspired and implemented this work. Professor Hermann Haus and Dr.  ... 
doi:10.1016/s0169-4332(00)00126-4 fatcat:t437qftyjzfpbfbg5oxoplpcqi

On the Area and Energy Scalability of Wireless Network-on-Chip: A Model-Based Benchmarked Design Space Exploration

Sergi Abadal, Mario Iannazzo, Mario Nemirovsky, Albert Cabellos-Aparicio, Heekwan Lee, Eduard Alarcon
2015 IEEE/ACM Transactions on Networking  
, and (b) the capacity of each link in the network.  ...  To this end, an integral design space exploration is performed, covering implementation aspects (area and energy), communication aspects (link capacity) and networklevel considerations (number of cores  ...  This work has been also partially supported by the FI-AGAUR grant of the Catalan Government and the FPU grant of the Spanish Ministry of Education.  ... 
doi:10.1109/tnet.2014.2332271 fatcat:tqomwzgajvd7dndi53pm45jrui

Exploitation of optical interconnects in future server architectures

A. F. Benner, M. Ignatowski, J. A. Kash, D. M. Kuchta, M. B. Ritter
2005 IBM Journal of Research and Development  
This paper reviews the various levels of a server interconnect hierarchy and the current status of optical interconnect technology for these different levels.  ...  of optical interconnects.  ...  *Trademark or registered trademark of International Business Machines Corporation.  ... 
doi:10.1147/rd.494.0755 fatcat:kn642j4yczc2nja77r2ejxo6xa

Rationale and challenges for optical interconnects to electronic chips

D.A.B. Miller
2000 Proceedings of the IEEE  
An Appendix analyzes scaling of on-chip global electrical interconnects, including line inductance and the skin effect, both of which impose significant additional constraints on future interconnects.  ...  It may allow continued scaling of existing architectures and enable novel highly interconnected or high-bandwidth architectures.  ...  This limit on the bit-rate capacity , of a simple line therefore depends only on the (architectural) "aspect ratio" of the line, by which we mean the ratio of the length of the line to its cross-sectional  ... 
doi:10.1109/5.867687 fatcat:dx3lmlicrje5vjrbbprdox7wfm

Experimental evaluation and comparison of time-multiplexed multi-FPGA routing architectures

Asmeen Kashif, Mohammed A. S. Khalid
2016 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS)  
are better capable of accommodating designs with higher connectivity count, there is still a fair chance that they can suffer from a lack of interconnect capacity due to limited number of input/output  ...  On the transmitter end, n-bit wide data from the internal domain is multiplexed by ωbit wide logic multiplexer which is inserted to accommodate the signals exceeding the transmission capacity.  ... 
doi:10.1109/mwscas.2016.7869975 dblp:conf/mwscas/KashifK16 fatcat:hgpls6pryvfvpnsbwnvxup6o34

Technologies for exascale systems

P. W. Coteus, J. U. Knickerbocker, C. H. Lam, Y. A. Vlasov
2011 IBM Journal of Research and Development  
To satisfy the economic drive for ever more powerful computers to handle scientific and business applications, new technologies are needed to overcome the limitations of current approaches.  ...  A combination of these technologies will likely be required to build exascale systems that meet the combined challenges of a practical power constraint on the order of 20 MW with sufficient reliability  ...  The manuscript benefitted from insightful suggestions of Dale Becker.  ... 
doi:10.1147/jrd.2011.2163967 fatcat:qxcybru7hfhqzdrn6msvkowwhi

Evaluating the Feasibility of Wireless Networks-on-Chip Enabled by Graphene

Sergi Abadal, Albert Mestres, Mario Iannazzo, Josep Solé-Pareta, Eduard Alarcón, Albert Cabellos-Aparicio
2014 Proceedings of the 2014 International Workshop on Network on Chip Architectures - NoCArc '14  
As we reach the manycore era, though, electrical interconnects present performance and power issues that are exacerbated in the presence of multicast communications due to the point-to-point nature of  ...  This dramatically limits the available design space in terms of manycore architecture, sparking the need for new solutions.  ...  The authors would like to thank Mario Nemirovsky, Max Lemme, Raúl Martínez and Ignacio Llatser for their invaluable research discussions.  ... 
doi:10.1145/2685342.2685345 dblp:conf/micro/AbadalMISAC14 fatcat:eot7yagb7zfctd5obid66zw2ma

Exascale Computing Technology Challenges [chapter]

John Shalf, Sudip Dosanjh, John Morrison
2011 Lecture Notes in Computer Science  
This article will describe the technology challenges on the road to exascale, their underlying causes, and their effect on the future of HPC system design.  ...  High Performance Computing architectures are expected to change dramatically in the next decade as power and cooling constraints limit increases in microprocessor clock speeds.  ...  The consequence of this observation is that natural bit rate capacity of the wire depends on the aspect ratio of the line, which is the ratio of the length to the cross-sectional area for a constant input  ... 
doi:10.1007/978-3-642-19328-6_1 fatcat:abivlcxkpzchrn2dgbg5qbzt4e

Scaling the capacity of memory systems; evolution and key approaches

Kyriakos Paraskevas, Andrew Attwood, Mikel Lujan, John Goodacre
2019 Proceedings of the International Symposium on Memory Systems - MEMSYS '19  
It is therefore important to understand that this demand and the consequential limitations in various aspects led to the appearance of new memory technologies and system designs.  ...  The demand on memory capacity from applications has always challenged the available technologies.  ...  The aspect ratio of the capacitor has sharply increased and will reach~100 shortly because of the aggressive scaling of DRAM.  ... 
doi:10.1145/3357526.3357555 dblp:conf/memsys/ParaskevasALG19 fatcat:qlsuo7csujg3rhbwf3efqljhta

A high-performance heterogeneous embedded signal processing system based on serial RapidIO interconnection

Wu Changrui, Cen Fan, Cai Huizhi
2010 2010 3rd International Conference on Computer Science and Information Technology  
The system is designed based from aspects of computation capability of single processor, scale of parallelism in system, arrangement of memory architecture, interconnection topology and bandwidth.  ...  The system can perform up to 2Gsps sampling rate, up to 550MHz processing capability on FPGA and 1.5GHz on CPU and up to 80Gbits/s aggregate bandwidth.  ...  higher ADC sampling rate and frequency resolution, adequate computation capacity and I/O bandwidth.  ... 
doi:10.1109/iccsit.2010.5564987 fatcat:viepqzrim5g3bl3hzqn6ewlcti

Optics in Computing: From Photonic Network-on-Chip to Chip-to-Chip Interconnects and Disintegrated Architectures

Theonitsa Alexoudi, Nikolaos Terzenidis, Stelios Pitris, Miltiadis Moralis-Pegios, Pavlos Maniotis, Christos Vagionas, Charoula Mitsolidou, George Mourgias-Alexandris, George T. Kanellos, Amalia Miliou, Konstantinos Vyrsokinos, Nikos Pleros
2019 Journal of Lightwave Technology  
of Postdoctoral Researchers", in the framework of the Operational Programme "Human Resources Development Program, Education and Lifelong Learning" of the National Strategic Reference Framework (NSRF)  ...  Alexoudi acknowledges support from the IKY scholarships program that is co-financed by the European Union (European Social Fund -ESF) and Greek national funds through the action entitled "Reinforcement  ...  Electronic SRAMs have opted for an increased access time from 150psec to 300psec in order to break the energy efficiency limit of 1fJ/bit as they moved from 45nm to 16nm technology [172] .  ... 
doi:10.1109/jlt.2018.2875995 fatcat:gxlflc7gfjfqrd7f3efmoiq3uy

A Universal Multi-Hierarchy Figure-of-Merit for On-Chip Computing and Communications [article]

Shuai Sun, Vikram K. Narayana, Armin Mehrabian, Tarek El-Ghazawi, Volker J. Sorger
2016 arXiv   pre-print
Continuing demands for increased compute efficiency and communication bandwidth have led to the development of novel interconnect technologies with the potential to outperform conventional electrical interconnects  ...  Since this FOM is derived bottom-up, we demonstrate remarkable adaptability to applications ranging from device-level to network and system-level.  ...  principle giving a maximum bit rate per unit mass of the system [41] .  ... 
arXiv:1612.02486v1 fatcat:52skd2goe5cffj6pqikowink4i
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