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Lightweight Implementations of SHA-3 Candidates on FPGAs
[chapter]
2011
Lecture Notes in Computer Science
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TP/Area (Mbps/LE)
Long Messages Short Messages Grøstl better than BLAKE on Cyclone ii. Small changes in ranking depending on device. ...
Hash Function Competition Previous Work Goal Our Goal: Comprehensive set of lightweight implementations of all Round 2 SHA-3 Candidates (except SIMD) and all SHA-3 Finalists. ...
/Area optimized implementations on FPGAs were published: Gaj et al.[CHES 2010], Matsuo et al.[SHA-3 conference 2010], Baldwin et al.[SHA-3 conference 2010]. ...
doi:10.1007/978-3-642-25578-6_20
fatcat:zt5upufb2faphhgryj2qzvdixi
FPGA implementation and DPA resistance analysis of a lightweight HMAC construction based on photon hash family
2013
2013 23rd International Conference on Field programmable Logic and Applications
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In order to cover this lack, a lightweight implementation of HMAC based on the Photon family of hash functions is given in this work. ...
Implementation and performance results for Xilinx Virtex-5 FPGAs of the HMAC structure is provided. ...
our knowledge, there are not results for HMAC imple-
mentations based on SHA-3 candidates. ...
doi:10.1109/fpl.2013.6645605
dblp:conf/fpl/EiroaB13
fatcat:54727z4gxfbjbc3bdhor6zmrae
Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates
2012
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. ...
The first contribution of our paper is that we propose a platform, a design strategy and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. ...
ACKNOWLEDGMENT The authors would like to thank Dai Watanabe from Hitachi Ltd, the designer of Luffa hash function, for providing valuable inputs regarding the classification of the SHA-3 candidates. ...
doi:10.1109/tvlsi.2011.2128353
fatcat:ma5vw44piffe5atllvs6qdx23i
Hardware authentication based on PUFs and SHA-3 2nd round candidates
2010
2010 International Conference on Microelectronics
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Implementation details are discussed in the case of Xilinx FPGAs. Index Terms-Hash function, lightweight protocol, physically unclonable function, true random number generator. ...
The second relevant block is a SHA-3 2 nd round candidate, a Secure Hash Algorithm (in particular Keccak), which has been proposed to replace the SHA-2 functions that have been broken no long time ago. ...
Implementation details are discussed in the case of Xilinx FPGAs. Index Terms-Hash function, lightweight protocol, physically unclonable function, true random number generator. ...
doi:10.1109/icm.2010.5696149
fatcat:m3lfe7gdsncqfmwa267jq3mvy4
A Comprehensive Framework for Fair and Efficient Benchmarking of Hardware Implementations of Lightweight Cryptography
[article]
2019
IACR Cryptology ePrint Archive
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of Round 2 and Round 3 CAESAR candidates. ...
Equipped with these resources, hardware designers can focus on implementing only a core functionality of a given algorithm. ...
This interface and protocol were then extended to the case of lightweight applications and applied to the implementations of 13 Round 2 and 5 Round 3 SHA-3 candidates [4] . ...
dblp:journals/iacr/KapsDTFHG19
fatcat:n7opl73bjrc3vffzxq3lpxwqqa
Embedded Syndrome-Based Hashing
[chapter]
2012
Lecture Notes in Computer Science
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We present novel implementations of the syndrome-based hash function RFSB on an Atmel ATxmega128A1 microcontroller and a low-cost Xilinx Spartan-6 FPGA. ...
Therefore, the National Institute of Standards and Technology (NIST) announced the public SHA-3 competition in the end of 2007 [36] . ...
We show that RFSB-509 can be efficiently implemented on both platforms and that RFSB can, in contrast to its predecessor FSB, keep up with current SHA-3 candidates and hash standards. ...
doi:10.1007/978-3-642-34931-7_20
fatcat:hvrp2sobhbabldqj3p5l7fdbhi
IPSecco: A lightweight and reconfigurable IPSec core
2012
2012 International Conference on Reconfigurable Computing and FPGAs
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Our results show that it is possible to realize a high performance IPSec core even on members of the Spartan-3 family. ...
Instead of re-implementing common IPSec configurations, which are deemed "too heavy" for pervasive devices, we evaluate efficient implementations of standardized and/or well-known lightweight and hardware-friendly ...
As hash functions we evaluate SHA-3 candidate GRØSTL [15] and the lightweight proposal PHOTON [16] , which uses the PRESENT Sbox. ...
doi:10.1109/reconfig.2012.6416757
dblp:conf/reconfig/DriessenGKMPP12
fatcat:35qy2aqsanhevhle7xbvgmuhwi
High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing
2022
International Journal of Power Electronics and Drive Systems (IJPEDS)
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(FPGA) devices and compared to existing FPGA implementations. ...
This approach allows us to design data paths of SHA-3 with higher Throughput and higher clock frequencies. ...
The selection of the candidates was based on various evaluation criteria, only 14 were chosen for the second round of the competition. Keccak has been selected as the SHA-3 standard [3] . ...
doi:10.11591/ijece.v12i2.pp1324-1333
fatcat:bs7dydhhdbecbdoi6x7gy7kdai
Compact implementations of BLAKE-32 and BLAKE-64 on FPGA
2010
2010 International Conference on Field-Programmable Technology
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We propose compact architectures of the SHA-3 candidates BLAKE-32 and BLAKE-64 for several FPGA families. ...
For the time being, the designs presented in this work are the most compact ones for any of the SHA-3 candidates. ...
table Flip - Flip flop
BX
XQ
X
F5
XB
F[4:1]
Table 3 . 3 Compact implementations of SHA-3 candidates on Xilinx Spartan-3 devices. ...
doi:10.1109/fpt.2010.5681776
dblp:conf/fpt/BeuchatOY10
fatcat:ewiqm5eatnfu3nfn5fmfowxhbu
The Hardware Implementation of NIST Lightweight Cryptographic Candidate SpoC for loT Devices
2021
International journal of advanced science and convergence. (Online)
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Background/Objectives: This paper presents the hardware implementation of SpoC Lightweight Cryptography (LWC) candidate for low-cost devices. ...
The design was implemented on the Virtex-4 Field FPGA using Xilinx ISE Design Suite. The synthesis results reported 951 slices at 246.61 MHz maximum clock frequency. ...
This work focuses on implementing a hardware architecture for one of the NIST lightweight AEAD candidates known as SpoC. ...
doi:10.22662/ijasc.2021.3.1.011
fatcat:tjdxp6s73zh4jlimhah3juut6u
A Lightweight Implementation of Keccak Hash Function for Radio-Frequency Identification Applications
[chapter]
2010
Lecture Notes in Computer Science
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In this paper, we present a lightweight implementation of the permutation Keccak-f [200] and Keccak-f[400] of the SHA-3 candidate hash function Keccak. ...
To the best of our knowledge, it is also the first lightweight implementation of a sponge function, which differentiates it from the previous works. ...
gate counts for fully parallel implementations of Keccak-
f[1600] and a few other SHA-3 candidates. ...
doi:10.1007/978-3-642-16822-2_20
fatcat:oyxahq7yfrebdejdmo2kdtwqoq
VLSI implementations of the cryptographic hash functions MD6 and ïrRUPT
2009
2009 IEEE International Symposium on Circuits and Systems
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This paper investigates VLSI architectures of the SHA-3 candidates MD6 and ïrRUPT. ...
While an average performance on highend processors is generally not critical, implementability and flexibility in hardware is crucial, because the new standard will be implemented in a variety of lightweight ...
To the best of the authors' knowledge this is the first paper that investigates hardware implementations of SHA-3 candidates. Outline: The remainder of this paper is organized as follows. Sec. ...
doi:10.1109/iscas.2009.5118412
dblp:conf/iscas/HenzenCAOF09
fatcat:gm2r7tftzvcg3iybtlr6n3zkyy
Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor
2018
IEICE transactions on information and systems
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This paper proposes two efficient SHA-3 ASIPs based on an open 32-bit RISC-V embedded processor named Z-scale. ...
Implementation results show that both proposed ASIPs can effectively accelerate SHA-3 algorithm with 14.6% and 26.9% code size reductions, 30% and 87% resource efficiency improvements, 71% and 262% better ...
ASIP design for SHA-3 has drawn attentions since the competition was launched. [15] explores acceleration of the SHA-3 candidate algorithms by doing ISE on a 16-bit PIC24 processor. ...
doi:10.1587/transinf.2017icp0019
fatcat:xrc7jkzypzghnmgmdz33ud445q
NIST Lightweight Cryptography Standardization Process: Classification of Second Round Candidates, Open Challenges, and Recommendations
2021
Journal of Information Processing Systems
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The paper presents an easy-to-understand comparative overview of the recommended parameters, primitives, mode of operation, features, security parameter, and hardware/software performance of the 32 candidate ...
The paper goes further by discussing the challenges of the Lightweight Cryptography Standardization Process and provides some suitable recommendations. ...
The reason for the high number of permutation-based candidates is that the winner of the Secure Hash Algorithm 3 (SHA-3) competition [20] is a permutation-based function known as Keccak [21] . ...
doi:10.3745/jips.03.0156
dblp:journals/jips/GookyiKR21
fatcat:ksqkmfcm4ncbtcja2ge5fmw3gm
Implementation and Benchmarking of Round 2 Candidates in the NIST Post-Quantum Cryptography Standardization Process Using Hardware and Software/Hardware Co-design Approaches
[article]
2020
IACR Cryptology ePrint Archive
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Winners of two past NIST cryptographic contests (Rijndael in case of AES and Keccak in case of SHA-3) were ranked consistently among the two fastest candidates when implemented using FPGAs and ASICs. ...
Using hardware also permits much higher flexibility in trading one subset of these properties for another. ...
In Round 2, all AES, all SHA-3, and all but one CAESAR candidates had at least one hardware implementation reported by the end of the evaluation process. ...
dblp:journals/iacr/DangFAMNG20
fatcat:l632lw4f6bgixfv2otzmpi7cmm
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