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Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

A.U. Diril, Y.S. Dhillon, A. Chatterjee, A.D. Singh
2005 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design.  ...  We propose a method of applying dual supply voltages at gate level granularity without using level shifters.  ...  In this paper, we propose a circuit technique to eliminate the need for additional level shifter use in dual supply CMOS circuit design.  ... 
doi:10.1109/tvlsi.2005.857149 fatcat:dzq46chqmzfrdkjhbz5i3xydgq

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

A.U. Diril, Y.S. Dhillon, Abhijit Chatterjee, A.D. Singh
18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design  
But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design.  ...  We propose a method of applying dual supply voltages at gate level granularity without using level shifters.  ...  In this paper, we propose a circuit technique to eliminate the need for additional level shifter use in dual supply CMOS circuit design.  ... 
doi:10.1109/icvd.2005.115 dblp:conf/vlsid/DirilDCS05 fatcat:id2p4kgtgfbfpniprzsmf3er3y

Low-power dual V th pseudo dual V dd domino circuits

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2004 Proceedings of the 17th symposium on Integrated circuits and system design - SBCCI '04  
Domino logic is a commonly used alternative to CMOS logic for designing circuits with high speed and/or low area requirements.  ...  We propose a novel low-power domino gate design and also a methodology to use these low-power but slower gates with regular domino logic gates in combinational circuits to achieve low-power operation without  ...  [6] use dual supply voltages and dual threshold voltages together with a low voltage swing clock in order to reduce power consumption of domino circuits.  ... 
doi:10.1145/1016568.1016640 dblp:conf/sbcci/DhillonDCS04 fatcat:x7rxozigdreldawbwxuxfeirlq

Trends in Design of Low Power Circuits Using Level Shifting Buffers for Multi Supply Systems

R. Sindhu R. Sindhu, Katamareddy Swapna Katamareddy Swapna, K. Nagendrakumar K. Nagendrakumar
2021 International Journal of Engineering Technology and Management Sciences  
Multiple supply voltage designs need voltage level conversions between multiple voltage domains. This is achieved by the application of voltage level shifter (LS) circuits.  ...  Numbers of methods were developed for reducing the power and delay by reducing supply voltage and multi supply voltages.  ...  The LS circuit described about importance of dual supply voltage design by a clustered voltage scaling (CVS) design is an efficient approach to decrease chip level power consumption.  ... 
doi:10.46647/ijetms.2021.v05i05.001 fatcat:jjb4vsynebbnxoi7ivoafxpuc4

Low-power domino circuits using NMOS pull-up on off-critical paths

Abdulkadir U. Diril, Yuvraj S. Dhillon, Abhijit Chatterjee, Adit D. Singh
2005 Proceedings of the 2005 conference on Asia South Pacific design automation - ASP-DAC '05  
We use a heuristic algorithm to replace the fast, high power gates on the off-critical paths with slower, low power gates while maintaining the circuit performance.  ...  Domino logic is used extensively in high speed microprocessor datapath design. Although domino gates have small propagation delay, they consume relatively more power.  ...  [3] use dual supply voltages and dual threshold voltages together with a low voltage swing clock in order to reduce power consumption of domino circuits.  ... 
doi:10.1145/1120725.1120956 dblp:conf/aspdac/DirilDCS05 fatcat:56a5rw7tcbhfpa4afpkmxfdn3m

Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation

Dipankar Saha, Aanan Chatterjee, Sayan Chatterjee, C. K. Sarkar
2014 Advances in Electrical Engineering  
Subthreshold circuit designs are very much popular for some of the ultra-low power applications, where the minimum energy consumption is the primary concern.  ...  A modified row-based dual Vdd 4-operand carry save adder (CSA) design has been reported in the present work using 45 nm technology.  ...  ., IC Design & Fabrication Centre, Jadavpur University, for giving them the opportunity to carry out this work using SPICE Tools.  ... 
doi:10.1155/2014/814975 fatcat:plgqncyujnbmta5c4rgkosekm4

Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates

Kyungseok Kim, Vishwani D. Agrawal
2011 2011 12th International Symposium on Quality Electronic Design  
This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages.  ...  Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage.  ...  A level-shifter free design using dual V th [4] places high V th devices in the pull-up PMOS network of a logic gate to suppress DC static leakage with low input signals as shown in Figure 3 .  ... 
doi:10.1109/isqed.2011.5770804 dblp:conf/isqed/KimA11 fatcat:rmrmgq2pfzegpbvac6tnuz2lxu

A CPL-based dual supply 32-bit ALU for sub 180nm CMOS technologies

Bhaskar Chatterjee, Manoj Sachdev, Ram Krishnamurthy
2004 Proceedings of the 2004 international symposium on Low power electronics and design - ISLPED '04  
In this paper we present the design of a high performance 32-bit ALU for low power applications. We use dual power supply scheme and CPL logic for non-critical units of the ALU.  ...  In addition, latches with only n-MOS clocked transistors are used to interface logic operating at different power supplies and achieve static power free operation.  ...  In section 3 we present circuit level techniques used in the ALU design to achieve low power operation.  ... 
doi:10.1145/1013235.1013298 dblp:conf/islped/ChatterjeeSK04 fatcat:vnhkhsajrbdptpgp4ykisjeuau

Near-Threshold Voltage Design Techniques for Heterogenous Manycore System-on-Chips

Sriram Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, James Tschanz, Vivek De
2020 Journal of Low Power Electronics and Applications  
the threshold voltage (VT) of the CMOS transistors.  ...  Aggressive power supply scaling into the near-threshold voltage (NTV) region holds great potential for applications with strict energy budgets, since the energy efficiency peaks as the supply voltage approaches  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/jlpea10020016 fatcat:wuwirnk4ljc7tjllpzc3ng7jei

A 10b 50MS/s 90nm CMOS skinny-shape ADC using variable references for CIS applications

Jun-Sang Park, Tai-Ji An, Yong-Min Kim, Suk-Hee Cho, Hyun-Sun Shim, Woo-Jin Jang, Yong-Jin Shin, Jun-Hyup Lee, Gil-Cho Ahn, Seung-Hoon Lee
2013 2013 International SoC Design Conference (ISOCC)  
The ADC with an active die area of 0.23mm 2 consumes 17.5mW at 50MS/s using dual supply voltages of 2.5V for analog and 1.2V for digital.  ...  The proposed on-chip I/V reference circuits generate the required variable reference voltages with a fixed common-mode level using a single external control voltage.  ...  Hence, analog circuits for the CIS commonly employ a high supply voltage of over 2.5V to acquire a high dynamic range, while digital circuits use a low supply voltage to minimize power consumption and  ... 
doi:10.1109/isocc.2013.6863990 fatcat:gfzfgyy2brgnda4tchkmurgbuu

Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation

Yuzuru Shizuku, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa, Mitsuji Okada
2015 IEICE Electronics Express  
We employ an asynchronous circuit design technique for low-voltage operations to achieve ultra-low power dissipation.  ...  In this paper, we present an ultra-low voltage Advanced Encryption Standard (AES) SubBytes transformation (S-BOX) circuit.  ...  Acknowledgments This work was partially supported by KAKENHI, the New Energy and Industrial Technology Development Organization (NEDO), and the VLSI Design and Education Center (VDEC), the University of  ... 
doi:10.1587/elex.12.20141157 fatcat:wymh77q6krei5gd5iaohfqvfsq

Simple Scheme for the Implementation of Low Voltage Fully Differential Amplifiers without Output Common-Mode Feedback Network

Mario Renteria-Pinon, Jaime Ramirez-Angulo, Alejandro Diaz-Sanchez
2020 Journal of Low Power Electronics and Applications  
It has a rail to rail output signal swing and high rejection of common-mode input signals. It operates in strong inversion with ±300 mV supplies in a 180 nm CMOS process.  ...  A simple scheme to implement class AB low-voltage fully differential amplifiers that do not require an output common-mode feedback network (CMFN) is introduced.  ...  Conflicts of Interest: The authors declare no conflict of interest.  ... 
doi:10.3390/jlpea10040034 fatcat:yhxc3dhw2vfvxcbjo3oo7ax5uy

A New Precision Peak Detector/Full-Wave Rectifier

Predrag B. Petrović
2013 Journal of Signal and Information Processing  
The proposed circuits use an all-pass filter as a 90˚ phase shifter of the processed input signal.  ...  The circuit gives a DC output voltage that is the peak input voltage over a wide frequency range, with a very low ripple voltage and low harmonic distortion.  ...  It is also possible to perform low-voltage (below threshold level of the diode) rectification using the proposed circuit.  ... 
doi:10.4236/jsip.2013.41009 fatcat:47qp6lx4izhdjisxocwyauqvby

2019 Index IEEE Transactions on Circuits and Systems I: Regular Papers Vol. 66

2019 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
Liu, X., A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS.  ...  ., +, TCSI June 2019 2124-2136 Delay circuits A New Design Technique for Sub-Nanosecond Delay and 200 V/ns Power Supply Slew-Tolerant Floating Voltage Level Shifters for GaN SMPS.  ...  Analysis of SRAM Enhancements Through Sense Amplifier  ... 
doi:10.1109/tcsi.2020.2966967 fatcat:f663jj5g45e3peggn3gwn5jys4

Process variation tolerant pipeline design through a placement-aware multiple voltage island design style

Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
This however comes at a significant power cost. We envision multi supply voltage design (MSV) as a promising technique to mitigate such power overhead.  ...  Then, during post-silicon testing the supply voltage of a proper number of voltage islands is raised depending on the actual violation scenario, thus bringing performance back within nominal values.  ...  level-shifter free chip-wide high-Vdd designs.  ... 
doi:10.1145/1403375.1403610 fatcat:wvp7ulhlwfdhxbyxmrsv5qnr6a
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