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Level oriented formal model for asynchronous circuit verification and its efficient analysis method

T. Kitai, Y. Oguro, T. Yoneda, E. Mercer, C. Myers
2002 Pacific Rim International Symposium on Dependable Computing, 2002. Proceedings.  
Using a level-oriented model for verification of asynchronous circuits helps users to easily construct formal models with high readability or to naturally model datapath circuits.  ...  This paper first introduces a level-oriented formal model based on time Petri nets, and then proposes its partial order reduction algorithm that prunes unnecessary state generation while guaranteeing the  ...  Conclusion This paper proposes a level-oriented model, LTN, for formal verification that naturally models the behavior of asynchronous circuits.  ... 
doi:10.1109/prdc.2002.1185640 dblp:conf/prdc/KitaiOYMM02 fatcat:bnbtg6xgizchxacf2hif2zhutm

Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs

Sandip Ray, Jay Bhadra, Magdy S. Abadir, Li-C Wang
2013 Journal of electronic testing  
There has been significant research on verification and testing chal-S. Ray ( )  ...  Consequently, verification and testing technology will continue to dominate as crucial factors in time-tomarket, reliability, and cost of VLSI systems.  ...  The first paper, "Observation-Oriented ATPG and Scan Chain Disabling for Capture Power Reduction" by Lung-Jen Lee, presents a method for reducing test power for testing integrated circuits.  ... 
doi:10.1007/s10836-013-5411-y fatcat:zfhwpkfkmfhivjtpsxsgu5wlry

Formal Specification and Verification of Communication in Network-On-Chip: An Overview

Fateh Boutekkouk
2018 International Journal of Recent Contributions from Engineering, Science & IT  
In this paper we try to giva an overview of the most famous formal methods applied to the verification of communication inside NOCs.  ...  Formal analysis of NOC communication will be very advantageous since it allows proving some theorems or interesting qualitative/quantitative properties on the communication behavior where simulation/emulation  ...  Invented by Jean-Raymond Abrial, the B method is a formal method for specification and verification of data oriented systems.  ... 
doi:10.3991/ijes.v6i4.9416 fatcat:7fljmcayfvdgpd7v3d4vt7lkvu

Verifying next generation electronic systems

Rolf Drechsler, Daniel Grose
2017 2017 International Conference on Infocom Technologies and Unmanned Systems (Trends and Future Directions) (ICTUS)  
In this paper the state-of-theart on verification is reported. Furthermore, recent developments are listed and finally the most pressing challenges for industry and academia are identified. I.  ...  Of course, for systems of the latter areas a thorough verification is required. However, due to increasing complexity, verification is still the major bottleneck. Hence, new approaches are required.  ...  However, formal verification of SystemC is very challenging due to its object oriented nature and event-driven simulation semantics [11] .  ... 
doi:10.1109/ictus.2017.8285965 fatcat:ajyzto3v7vhqbnr2xmqakmmzb4

Model checking

Edmund M. Clarke, E. Allen Emerson, Joseph Sifakis
2009 Communications of the ACM  
Model Figure 6: The CEGAR Loop for sequential circuits called the localization reduction, which was developed by R.  ...  Initial Abstraction Simulator No error or bug found Property holds Simulation sucessful Bug found Abstraction refinement Refinement Model Checker Verification Spurious counterexample Counterexample Abstract  ...  Today, we can specify and verify only high-level timed models with tools such as Uppaal [3] for schedulability analysis.  ... 
doi:10.1145/1592761.1592781 fatcat:4gjaorwdd5a25jeyoyethnw3fy

Model Checking Safety-Critical Systems Using Safecharts

Pao-Ann Hsiung, Yean-Ru Chen, Yen-Hung Lin
2007 IEEE transactions on computers  
To bridge this gap, we propose a model-based formal verification technique for safety-critical systems.  ...  In this work, the model-checking paradigm is applied to the Safecharts model, which was used for modeling but not yet used for verification.  ...  For the above reasons, we will thus employ a widely popular formal verification method called model checking for the verification of safety-critical systems that are formally modeled.  ... 
doi:10.1109/tc.2007.1021 fatcat:gto4nyvwfzgdvfqo4byvyngc7y

Translating concurrent action oriented specifications to synchronous guarded actions

Jens Brandt, Klaus Schneider, Sandeep K. Shukla
2010 SIGPLAN notices  
Concurrent Action-Oriented Specifications (CAOS) model the behavior of a synchronous hardware circuit as asynchronous guarded actions at an abstraction level higher than the Register Transfer Level (RTL  ...  We also show that our method simplifies formal verification of hardware synthesized from CAOS specifications over previously known formal verification approaches.  ...  Concurrent Action-Oriented Specifications [10] model the behavior of a hardware circuit as guarded actions at an abstraction level higher than the RTL.  ... 
doi:10.1145/1755951.1755896 fatcat:cq6vvljzajg57lmjk6h2z736uu

Formal Methods for the Synthesis of Biomolecular Circuits (Dagstuhl Seminar 18082)

Yaakov Benenson, Neil Dalchau, Heinz Koeppl, Oded Maler, Michael Wagner
2018 Dagstuhl Reports  
This report documents the program and the outcomes of Dagstuhl Seminar 18082 "Formal Methods for the Synthesis of Biomolecular Circuits".  ...  Hence, although circuits in synthetic biology are still by far less understood and characterized than electronic circuits, the opportunity for the formal synthesis of circuit designs with respect to a  ...  Using object orientation and asynchronous communication yields a model that captures bio-chemical concepts in a natural manner at the level of domain experts.  ... 
doi:10.4230/dagrep.8.2.88 dblp:journals/dagstuhl-reports/BenensonDKM18 fatcat:gh3poeii3ndmffhuiax3bf2pfu

Verification of electronic systems

Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha
1996 Proceedings of the 33rd annual conference on Design automation conference - DAC '96  
A design methodology should on one hand put to good use all techniques and methods developed thus far for verification, from formal verification to simulation, from visualization to timing analysis, but  ...  Hence Esterel by itself can only be used for process level modeling while the system level modeling of asynchronous communicating processes should be done using another formalism.  ... 
doi:10.1145/240518.240539 dblp:conf/dac/Sangiovanni-VincentelliMS96 fatcat:52fgmr2625ebvfemmbmaizxzbu

Model-Driven Development Meets Security: An Evaluation of Current Approaches

K Kasal, J Heurix, T Neubauer
2011 2011 44th Hawaii International Conference on System Sciences  
level, (ii) the user can build on the knowledge of experts, and (iii) the available tools are more efficient and powerful.  ...  Deficiencies in software design are the main reasons for security incidents, resulting in severe economic consequences for (i) the organizations using the software and (ii) the development companies.  ...  Acknowledgments This work was supported by grants of the Austrian Government's BRIDGE Research Initiative (contract 824884), the FIT-IT Research Initiative (contract 816158) and was performed at the research  ... 
doi:10.1109/hicss.2011.310 dblp:conf/hicss/KasalHN11 fatcat:eujsqve6ovgpbagm6nmftoi7li

Application and Verification of Local Nonsemantic-Preserving Transformations in System Design

Tarvo Raudvere, Ingo Sander, Axel Jantsch
2008 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
for each nonsemantic-preserving transformation, and 2) the global influence of the refinement to the entire system is studied through static analysis.  ...  Nonsemantic-preserving transformations introduce lower level implementation details, which are necessary to yield an efficient implementation.  ...  It is used to prepare a synchronous model for mapping to an asynchronous implementation.  ... 
doi:10.1109/tcad.2008.923249 fatcat:rmtkirn665gm7fq2ya7fggmwbm

Synchronous Programming (Dagstuhl Seminar 13471)

Stephen A. Edwards, Alain Girault, Klaus Schneider, Marc Herbstritt
2014 Dagstuhl Reports  
techniques, software and hardware architectures, as well as extensions, transformations, and interfaces to other models of computations, in particular to asynchronous and hybrid systems.  ...  For this reason, the synchronous composition is deterministic, which is a great advantage concerning predictability, verification of system design, and embedded code generation.  ...  This talk introduces some concepts of the coordination language AstraKahn which can be used for programming synchronous and asynchronous systems within the same framework.  ... 
doi:10.4230/dagrep.3.11.117 dblp:journals/dagstuhl-reports/EdwardsGS13 fatcat:b7aq6w2q4fawjjqtlfleujr3gi

Object-oriented modelling and specification using SHE

M.C.W. Geilen, J.P.M. Voeten, P.H.A. van der Putten, L.J. van Bokhoven, M.P.J. Stevens
2001 Computer languages  
The formal semantics of POOSL provides a solid basis for the application of verification and performance analysis techniques and establishing a rigorous connection to existing analysis tools.  ...  The (formal) system-level modelling language called POOSL is very expressive and is able to model dynamic hard real-time behaviour and to (visually) capture static (architecture and topology) structure  ...  The formal semantics of POOSL provides a solid basis for the application of verification and performance analysis techniques and establishing a rigorous connection to existing analysis tools.  ... 
doi:10.1016/s0096-0551(01)00014-5 fatcat:fwr7434zdvhqpdwgjljqwyuygm

Formal verification of hardware correctness: introduction and survey of current research

P. Camurati, P. Prinetto
1988 Computer  
In particular, we would like to thank Dominique Borrione, Mario Barbacci, Hans Eveking, and the referees for their help in reviewing the article, their suggestions, and their valuable cooperation.  ...  Acknowledgments We are grateful to all those people who kindly provided us with the papers, reports, and material used throughout this article.  ...  For example, formal systems especially intended to model synchronous circuits are not easily extendible to asynchronous ones, and vice versa.  ... 
doi:10.1109/2.65 fatcat:dn5xh3m4gbacfffc5ogxybxbjm

The Synchronous Approach to Reactive and Real-Time Systems Manuscript received September 15, 1990; revised March 9, 1991. IEEE Log Number 9102298 [chapter]

ALBERT BENVENISTE, GÉRARD BERRY
2002 Readings in Hardware/Software Co-Design  
This makes it possible to handle compilation, logical correctness proofs, and verifications of real-time programs in a formal way, leading to a clean and precise methodology for design and programming.  ...  The major concern of the synchronous approach is to base synchronous programming languages on mathematical models.  ...  Clarke for his careful reading and criticism of the manuscript.  ... 
doi:10.1016/b978-155860702-6/50013-2 fatcat:q5na5q5pjzapjfmqj4nyowhnja
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