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Implementing branch-predictor decay using quasi-static memory cells

Philo Juang, Kevin Skadron, Margaret Martonosi, Zhigang Hu, Douglas W. Clark, Philip W. Diodato, Stefanos Kaxiras
2004 ACM Transactions on Architecture and Code Optimization (TACO)  
For these reasons, it is natural to consider applying decay techniques-already shown to reduce leakage energy for caches-to branch-prediction structures.  ...  With semiconductor technology advancing toward deep submicron, leakage energy is of increasing concern, especially for large on-chip array structures such as caches and branch predictors.  ...  Margaret Martonosi and Doug Clark's research on energy-efficient processors is supported in part by NSF ITR grant CCR-0086031.  ... 
doi:10.1145/1011528.1011531 fatcat:d4kzsf5lyvbezpmlf7us445oyy

Managing leakage for transient data: decay and quasi-static 4T memory cells

Zhigang Hu, Philo Juang, P. Diodato, S. Kaxiras, K. Skadron, M. Martonosi, D.W. Clark
2002 Proceedings of the International Symposium on Low Power Electronics and Design  
In this paper we propose the use of quasi-static four-transistor (4T) RAM cells. Quasi-static 4T cells provide both energy and area savings.  ...  Overall, 4T-based branch predictors offer 12-33% area savings and 60-80% leakage savings with minimal performance impact.  ...  At such rates, leakage energy would balloon to 50% or more of total chip energy in just a few generations.  ... 
doi:10.1109/lpe.2002.146708 fatcat:6lxb4tlkvbdjhpurnxdnonrw6a

Prefetching-aware cache line turnoff for saving leakage energy

Ismail Kadayif, Mahmut Kandemir, Feihui Li
2006 Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06  
Our experiments with applications from the SPEC2000 suite indicate that the proposed approaches save significant leakage energy with very small degradation on performance.  ...  While numerous prior studies focused on performance and energy optimizations for caches, their interactions have received much less attention.  ...  To explain this strategy better, let us consider the Figure 2(c) . The cache line is brought into the cache via prefetching at time t4.  ... 
doi:10.1145/1118299.1118351 fatcat:mg2uchm6dffwzjwjmwgrb6c3kq

Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems [chapter]

Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson
2009 Lecture Notes in Computer Science  
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures.  ...  As growing cache sizes consume larger portions of the die, reducing their power consumption becomes increasingly important.  ...  exploits locality behavior of the different data regions.  ... 
doi:10.1007/978-3-642-00904-4_5 fatcat:o2do5vhuarh3na2kjnv6h2pvm4

Reducing instruction cache energy consumption using a compiler-based strategy

W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin
2004 ACM Transactions on Architecture and Code Optimization (TACO)  
This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach.  ...  We also evaluate the sensitivity of these optimizations to different high-level compiler transformations, energy parameters, and soft errors.  ...  These numbers indicate that our strategies are very effective in exploiting the idleness of cache lines for potential leakage energy savings.  ... 
doi:10.1145/980152.980154 fatcat:2wucg7vewzaofhnmivcxvhlvlq

Reducing leakage power in peripheral circuits of L2 caches

Houman Homayoun, Alex Veidenbaum
2007 2007 25th International Conference on Computer Design  
They primarily target the leakage in the peripheral circuitry of an L2 cache and as such have to be able to cope with longer delays.  ...  One technique exploits the fact that processor activity decreases significantly after an L2 cache miss occurs and saves power during L2 miss service time.  ...  Kaxiras et al. proposed a cache decay technique which reduces cache leakage by turning off cache lines not likely to be reused [8] .  ... 
doi:10.1109/iccd.2007.4601907 dblp:conf/iccd/HomayounV07 fatcat:llcrpba5ojewjlwpvkk5zitsu4

LEMap: Controlling leakage in large chip-multiprocessor caches via profile-guided virtual address translation

Jugash Chandarlapati, Mainak Chaudhuri
2007 2007 25th International Conference on Computer Design  
In this paper, with the aim of reducing leakage energy we introduce LEMap (Low Energy Map), a novel virtual address translation scheme to control the set of physical pages mapped to each bank of a large  ...  suites shows that LEMap, on average, saves 7% of total energy, 50% of L2 cache energy, and 52% of L2 cache power while suffering from a 3% loss in performance compared to a baseline system that employs  ...  We thank Vijay Degalahal of Intel for helping us with HSPICE and Arkaprava Basu for initial help with the clustering algorithms.  ... 
doi:10.1109/iccd.2007.4601934 dblp:conf/iccd/ChandarlapatiC07 fatcat:ukqgwk7opfcbzgkj64q32p3dxa

An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques [chapter]

Ivan Ratković, Nikola Bežanić, Osman S. Ünsal, Adrian Cristal, Veljko Milutinović
2015 Advances in Computers  
Both computer architects and circuit designers intent to reduce power and energy (without a performance Advances in Computers, Volume 98 # 2015 Elsevier Inc.  ...  Power dissipation and energy consumption became the primary design constraint for almost all computer systems in the last 15 years.  ...  Polychronopoulos [43] "HotSpot cache: joint temporal and spatial locality exploitation for I-cache energy reduction," C. Yang and C.H.  ... 
doi:10.1016/bs.adcom.2015.04.001 fatcat:5voowf7sizcpxaumb74nelc25a

Managing leakage for transient data

Zhigang Hu, Philo Juang, Phil Diodato, Stefanos Kaxiras, Kevin Skadron, Margaret Martonosi, Douglas W. Clark
2002 Proceedings of the 2002 international symposium on Low power electronics and design - ISLPED '02  
In this paper we propose the use of quasi-static four-transistor (4T) RAM cells. Quasi-static 4T cells provide both energy and area savings.  ...  Overall, 4T based branch predictors offers 12-33% area savings and 60-80% leakage savings with minimal performance impact.  ...  At such rates, leakage energy would balloon to 50% or more of total chip energy in just a few generations.  ... 
doi:10.1145/566408.566423 dblp:conf/islped/HuJDKSMC02 fatcat:nec3f7hpo5asdkwfrq5yqy3kmq

Exploring Energy Scalability in Coprocessor-Dominated Architectures for Dark Silicon

Qiaoshi Zheng, Nathan Goulding-Hotta, Scott Ricketts, Steven Swanson, Michael Bedford Taylor, Jack Sampson
2014 ACM Transactions on Embedded Computing Systems  
We show that scaling CoDAs to include very large numbers of coprocessors is challenging because of the energy cost of interconnects, the memory system, and leakage.  ...  The article presents a detailed study of energy costs across a wide range of tiled CoDA designs and shows that careful choice of cache configuration, tile size, coarse-grain power management and transistor  ...  To reduce the area cost of replication we can exploit the fact that, in most cases, applications will need the "spare" c-cores infrequently.  ... 
doi:10.1145/2584657 fatcat:pvkgf2jbynf7zkdw2257y6zq2y

Adaptive timekeeping replacement

Carole-Jean Wu, Margaret Martonosi
2011 ACM Transactions on Architecture and Code Optimization (TACO)  
This is the first detailed study of shared cache capacity management considering thread behaviors in parallel applications.  ...  The key novelties of our work are (1) ATR offers a complete cache capacity management framework taking into account application priorities and memory characteristics, and (2) ATR's fine-grained cache capacity  ...  We first give background on cache decay's original use for leakage control. Cache Decay Cache decay exploits the generational behavior of data stored in a cache.  ... 
doi:10.1145/1952998.1953001 fatcat:4iyejybvfrgnzi65zvkcr5ix7y

Branch prediction on demand

Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
We propose a methodology to reduce the energy consumption of the branch predictor by characterizing prediction demand using profiling and dynamically adjusting predictor resources accordingly.  ...  Detailed simulations show that this approach reduces the energy consumption in the branch predictor by an average of 72% and up to 89% with virtually no impact on prediction accuracy and performance.  ...  Hu et. al. let entries that are unused for a long time decay [7] . This reduces leakage energy of branch predictor.  ... 
doi:10.1145/871597.871603 fatcat:x7omqixyw5ftfig7f3s7pcsfe4

Branch prediction on demand

Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado, Michael C. Huang
2003 Proceedings of the 2003 international symposium on Low power electronics and design - ISLPED '03  
We propose a methodology to reduce the energy consumption of the branch predictor by characterizing prediction demand using profiling and dynamically adjusting predictor resources accordingly.  ...  Detailed simulations show that this approach reduces the energy consumption in the branch predictor by an average of 72% and up to 89% with virtually no impact on prediction accuracy and performance.  ...  Hu et. al. let entries that are unused for a long time decay [7] . This reduces leakage energy of branch predictor.  ... 
doi:10.1145/871506.871603 dblp:conf/islped/ChaverPPTH03 fatcat:todlb2lqzraxdgpjndnl7pd5ae

Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs

Mrinmoy Ghosh, Hsien-Hsin S. Lee
2007 Microarchitecture (MICRO), Proceedings of the Annual International Symposium on  
The simulation results show that our technique can reduce up to 86% of all refresh operations and 59.3% on the average for a 2GB DRAM.  ...  The overall energy saving in the DRAM is up to 25.7% with an average of 12.13% obtained for SPLASH-2, SPECint2000, and Biobench benchmark programs simulated on a 2GB DRAM.  ...  This research was supported by NSF Grant CNS-0325536, an NSF CAREER Award (CNS-0644096) and the C2S2 center of the Focus Center Research Program.  ... 
doi:10.1109/micro.2007.4408251 fatcat:pijx42duxbesdmaqy2jyedgfja

DVSleak

Yifan Zhu, Frank Mueller
2007 SIGPLAN notices  
Experiments show that this combined DVS/leakage algorithm results in an average of (a) 50% additional energy savings over a leakage-oblivious DVS algorithm, (b) 20% more energy savings over a more simplistic  ...  This makes DVSleak the best combined DVS/leakage regulation approach for real-time systems that we know of.  ...  Combining DVS and Leakage Savings To further exploit the savings for both static and dynamic power, we adapt the schedule of the system to reduce static leakage as much as possible.  ... 
doi:10.1145/1273444.1254772 fatcat:7janzocg3zcvhovmr47pyj4phq
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