235 Hits in 6.0 sec

A computational model for analytic column stores [article]

Eyal Rozenberg
2019 arXiv   pre-print
The model is based on circuits whose wires carry columns rather than scalar values, and whose nodes apply operators with column inputs and outputs.  ...  the column store maintaining significant out-of-plan data.  ...  The author particularly wishes to thank Prof. Dr. Peter Boncz, for his guidance and insights during that time. Finally, the author wishes to thank Profs. Drs.  ... 
arXiv:1904.12217v2 fatcat:3rehuab3fne4xb32guwgkhmxc4

IP Lookup Using the Novel Idea of Scalar Prefix Search with Fast Table Updates

Mohammad BEHDADFAR, Hossein SAIDI, Masoud-Reza HASHEMI, Ali GHIASIAN, Hamid ALAEI
2010 IEICE transactions on information and systems  
As a result, the search procedure complexity would be O(log n) where n is the number of prefixes stored in the tree.  ...  Here, it is assumed that interface to memory is wide enough to access the prefix and some simple operations like comparison can be done in O( 1 ) even for the word length w.  ...  Acknowledgments The authors wish to thank the anonymous reviewers for their valuable and helpful comments.  ... 
doi:10.1587/transinf.e93.d.2932 fatcat:7rgqcdhqsrclrhakytoor7p73i

Facilitating Preemptive Hardware System Design Using Partial Reconfiguration Techniques

Julio Dondo Gazzano, Fernando Rincon, Carlos Vaderrama, Felix Villanueva, Julian Caba, Juan Carlos Lopez
2014 The Scientific World Journal  
In FPGA-based control system design, partial reconfiguration is especially well suited to implement preemptive systems.  ...  This paper provides a hardware-based approach to explicit and implicit activation of the partial reconfiguration process in dynamically reconfigurable SoCs and includes all the necessary tasks to cope  ...  The time consumed storing DES state, according to (2) and considering a size state of 4 words of 32 bits (the encryption key and the two memory pointers), is without using burst state trf = 4 × 33 + 8  ... 
doi:10.1155/2014/164059 pmid:24672292 pmcid:PMC3932836 fatcat:4oj44sjxl5dpflj7aozylwy7gu

Dynamics of Bitcoin mining [article]

Nemo Semret
2022 arXiv   pre-print
We give precise answers based on the technical forces and incentives in the system. We then build on these dynamics to consider value: what is the cost and purpose of mining, and is it worth it?  ...  From first principles, we derive a fundamental scale-invariant feasibility constraint, which enables us to analyze the interlocking dynamics, find key invariants, and answer these questions mathematically  ...  Mining provides the ability to store and transfer value.  ... 
arXiv:2201.06072v2 fatcat:qlptkeuzrjbsnlal7rktzs4kxq

An Unbiased MCMC FPGA-Based Accelerator in the Land of Custom Precision Arithmetic

Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis
2017 IEEE transactions on computers  
In this work, a novel FPGA-based construction is proposed that utilises the custom precision support of FPGA devices in order to accelerate the computations, guaranteeing at the same time asymptotically  ...  Current approaches, based on multi-core CPUs, GPUs, and FPGAs, aim to accelerate the execution time of the MCMC methods using subsampling techniques or custom precision arithmetic, resulting to biased  ...  Firstly, we use Gappa++ to obtain the rounding error ε 2 of the dot product operation inside the exponent operation. Then we add ε 2 to the custom precision dot product values.  ... 
doi:10.1109/tc.2016.2630682 fatcat:u4g7hrmmpvazja6dc4kdcyk2cu

The Implementation of Texture-Based Video Up-Scaling on Coarse-Grained Reconfigurable Architecture

Rui SHI, Shouyi YIN, Leibo LIU, Qiongbing LIU, Shuang LIANG, Shaojun WEI
2015 IEICE transactions on information and systems  
We fully exploit the characters of TBVU and utilize several techniques to reduce memory I/O operation and total execution time.  ...  Video Up-scaling is a hotspot in TV display area; as an important brunch of Video Up-scaling, Texture-Based Video Upscaling (TBVU) method shows great potential of hardware implementation.  ...  The Interpolation (InterP) step computes the pixel value for each target new interpolated pixel. Table 1 1 Key parameters of REMUS. Table 2 2 Key parameters of TD.  ... 
doi:10.1587/transinf.2014rcp0010 fatcat:nphv57vtrvf5hbphxukrv54z3e

A noise bifurcation architecture for linear additive physical functions

Meng-Day Yu, David M'Raihi, Ingrid Verbauwhede, Srinivas Devadas
2014 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)  
Physical Unclonable Functions (PUFs) allow a silicon device to be authenticated based on its manufacturing variations using challenge/response evaluations.  ...  We present supporting data using 28nm FPGA PUF noise results as well as machine learning attack results.  ...  Delay propagation is mimicked by using digital logic to add an appropriate delay value for each stage depending on the challenge bit associated with that stage.  ... 
doi:10.1109/hst.2014.6855582 dblp:conf/host/YuMVD14 fatcat:ypcshivzw5g7fmvkol47v2oniu

Vision-Based Egomotion Estimation on FPGA for Unmanned Aerial Vehicle Navigation

Maria E. Angelopoulou, Christos-Savvas Bouganis
2014 IEEE transactions on circuits and systems for video technology (Print)  
This work presents a system architecture that employs a Field Programmable Gate Array (FPGA) as the main processing platform connected to a low-power CPU that targets the problem of vision-based egomotion  ...  However, the high computational requirements of vision-based egomotion algorithms, combined with the real-time performance and low power consumption requirements that are related to such an application  ...  ACKNOWLEDGMENT The research leading to these results was co-funded by the Technology Strategy Board UK.  ... 
doi:10.1109/tcsvt.2013.2291356 fatcat:bytn37re45da5khkdf6ctfp6be

Development and analysis of the new hashing algorithm based on block cipher

Kairat Sakan, Saule Nyssanbayeva, Nursulu Kapalova, Kunbolat Algazy, Ardabek Khompysh, Dilmukhanbet Dyusenbayev
2022 Eastern-European Journal of Enterprise Technologies  
hash functions based on block ciphers.  ...  This paper proposes the new hash algorithm HBC-256 (Hash based on Block Cipher) based on the symmetric block cipher of the CF (Compression Function).  ...  At this step, the new value i j c passes through the substitution S-box (SBOX procedure) to be stored in the same place as the new value of the matrix А.  ... 
doi:10.15587/1729-4061.2022.252060 fatcat:67ljh3jijvafbes6vfgwadxmfq

Performance Evaluation of Android Pattern Authentication Systems

Robert Wang, Stephan Chan, Yung-Cheng Chang
2019 Zenodo  
Therefore this research presents an alternative representation for mobile patterns using elliptic curves, and proposes three algorithms based on this ideology to make the pattern passwords strong against  ...  Android Kit Kat and Lollipop pattern authentication systems are vulnerable to pre-computations since they use SHA-1 unsalted hashes.  ...  STEP 2: To build this message a 64-bit value, turn round the two halves and add them to pad the string. STEP 3: Spot this message as a Salt value SHA-1.  ... 
doi:10.5281/zenodo.3774820 fatcat:i7chpcedtrfojpmwrfhue5o7ty

Final Statements [chapter]

2009 FPGA-Based Implementation of Signal Processing Systems  
The authors would like to thank Richard Walke and John Gray for motivating a lot of the work at Queen's University Belfast on FPGA.  ...  A number of other people have also acted to contribute in many other ways to either provide technical input or support. These  ...  The principle of the technique is based on the assumption that we will store the computed values rather than carry out the computation (as FPGAs have a readily supply of LUTs).  ... 
doi:10.1002/9780470713785.ch14 fatcat:b5uyg6k2qbhnncscazm2ickxki

An On-Chip AHB Bus Tracer With Real-Time Compression and Dynamic Multiresolution Supports for SoC

Fu-Ching Yang, Yi-Ting Lin, Chung-Fu Kao, Ing-Jer Huang
2011 IEEE Transactions on Very Large Scale Integration (vlsi) Systems  
In addition, it allows users to switch the trace resolution dynamically so that appropriate resolution levels can be applied to different segments of the trace.  ...  As a case study, it has been integrated into a 3-D graphics SoC to facilitate the debugging and monitoring of the system behaviors.  ...  The BSM is designed based on the AMBA AHB 2.0 protocol to represent the key bus handshaking activities within a transaction.  ... 
doi:10.1109/tvlsi.2009.2039811 fatcat:bhm2tw2z4jhuhddgqlibn42xgi

IoT Vertical Applications and Associated Security Requirements [chapter]

Sunil Cheruvu, Anil Kumar, Ned Smith, David M. Wheeler
2019 Demystifying Internet of Things Security  
DUKPT is a method to manage the key between two endpoints; this key has properties: unique per transaction, symmetric, is a derived key from Base Derivation Key (BDK) known to both endpoints.  ...  GUARD EXTENSION fTPM enables cryptographic keys to be securely stored in tampered-resistant keys vault PKI BASED ID (PTT ENDORSEMENT KEY) Utilize unique HW based key for secure channel establishment  ... 
doi:10.1007/978-1-4842-2896-8_6 fatcat:eznovqjwwbbn5a4czv3q5cj3cm

Joint Symbol and Chip Synchronization for a Burst-Mode-Communication Superregenerative MSK Receiver

Alexis Lopez-Riera, Francisco del Aguila-Lopez, Pere Pala-Schonwalder, Jordi Bonet-Dalmau, Rosa Giralt-Mas, F. Xavier Moncunill-Geniz
2017 IEEE Transactions on Circuits and Systems Part 1: Regular Papers  
The receiver is based on an SR oscillator which provides samples of the incoming instantaneous phase trajectories.  ...  We provide details on a VHDL implementation on an FPGA where the most complex digital processing block is an accumulator.  ...  ACKNOWLEDGMENT The authors would like to thank the Associate Editor and the anonymous reviewers for their helpful comments as they greatly improved this paper.  ... 
doi:10.1109/tcsi.2016.2636022 fatcat:ni5wyiscdvfd7azwxfamvq722a

GAMT: A fast and scalable IP lookup engine for GPU-based software routers

Yanbiao Li, Dafang Zhang, Alex X. Liu, Jintao Zheng
2013 Architectures for Networking and Communications Systems  
However, it is still a challenging task to deploy some core routing functions into GPU-based software routers with anticipatory performance and scalability, such as IP address lookup.  ...  According to our experiments on real-world routing data, based on the multi-stream pipeline, GAMT enables lookup speeds as high as 1072 and 658 Million Lookups Per Second (MLPS) for IPv4/6 respectively  ...  for SRAM-based pipeline on the FPGA [4] .  ... 
doi:10.1109/ancs.2013.6665171 dblp:conf/ancs/LiZLZ13 fatcat:kikkhakkt5b6pkswceujywlvie
« Previous Showing results 1 — 15 out of 235 results