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Leakage-tolerant design techniques for high performance processors

Vivek De
2002 Proceedings of the 2002 international symposium on Physical design - ISPD '02  
In addition, leakage-tolerant high performance circuits must be used to provide adequate circuit robustness. The most effective design technique for reducing leakage power is dual-V T design.  ...  Therefore, high performance and low power processor designs must employ leakage power control techniques to alleviate active power dissipation and delivery challenges, extend battery life and prevent thermal  ...  In addition, leakage-tolerant high performance circuits must be used to provide adequate circuit robustness. The most effective design technique for reducing leakage power is dual-V T design.  ... 
doi:10.1145/505388.505396 dblp:conf/ispd/De02 fatcat:tieveg3ysvf7bmqr6duygydkfe

Robust low power computing in the nanoscale era

Todd Austin
2006 Proceedings of the 19th annual symposium on Integrated circuits and systems design - SBCCI '06  
"… "… left unchecked, power consumption will left unchecked, power consumption will reach 1200 Watts for high reach 1200 Watts for high--end processors in end processors in 2018. 2018 … … the ability  ...  Design Techniques Fault Tolerant Design Techniques Robust Low Power Design Techniques Robust Low Power Design Techniques • • Better Better--Than Worst Case Design Concepts Than Worst Case Design  ... 
doi:10.1145/1150343.1150352 dblp:conf/sbcci/Austin06 fatcat:7cdhgdke4raevpc7m2plec6fjq

Guest Editorial Special Issue on Nanoelectronic Circuit and System Design Methods for the Mobile Computing Era

Aida Todri-Sanial, Saraju P. Mohanty, Mariane Comte, Marc Belleville
2017 ACM Journal on Emerging Technologies in Computing Systems  
This special issue describes six articles covering topics from emerging technologies for devices, memories, architecture to processor design for energy efficiency and high performance.  ...  Sartor et al., present several design techniques for very long instruction word (VLIW) processors to mitigate soft errors introduced due to technology scaling.  ... 
doi:10.1145/3003370 fatcat:7kw7ei7tnnas3jqgxke73rakiy

Modified Keeper Controlled Domino Circuit for Low Power High Performance Wide Fan in OR Gates

2019 International Journal of Engineering and Advanced Technology  
A novel modified keeper technique has been proposed in this paper for domino logic circuits implemented as wide fan in OR gate.  ...  The simulations were performed using 90nm PTM low power models.  ...  Novel designs are essential to cope up with such advanced circuitry and also for better battery optimizations. Leakage current replica technique or LCR [22] is given in Fig. 3 .  ... 
doi:10.35940/ijeat.f9168.088619 fatcat:c3n65xjajvb2teo5oubs6jfwci

Process variation tolerant pipeline design through a placement-aware multiple voltage island design style

Bonesi Stefano, Davide Bertozzi, Luca Benini, Enrico Macii
2008 Proceedings of the conference on Design, automation and test in Europe - DATE '08  
A common technique to compensate process variation induced performance deviations during post-silicon testing consists of the dynamic adaptation of processor voltage.  ...  Voltage islands are generated by exploiting cell proximity for minimal perturbation of performance pre-optimized placements.  ...  Target VLIW Architecture Based on the above model, we assessed the impact of process variations on the design of a processor core and the cost for variation tolerant design techniques.  ... 
doi:10.1145/1403375.1403610 fatcat:wvp7ulhlwfdhxbyxmrsv5qnr6a

Technology impacts on sub-90nm CMOS circuit design & design methodologies

R. Puri, T. Karnik, R. Joshi
2006 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)  
On the design front, researchers are exploring various circuit design techniques to deal with process variation, leakage and soft errors.  ...  scaling of the CMOS devices deep into sub-90nm technologies, fully depleted SOI, strained-Si on SiGe, FinFETs with double gate, and even further, three-dimensional circuits will be utilized to design high-performance  ...  He was elected as an IEEE fellow in 2002 for contributions to chip metallurgy materials and processes, and high performance processor and circuit design.  ... 
doi:10.1109/vlsid.2006.156 dblp:conf/vlsid/PuriKJ06 fatcat:jtuc263pjbf2jeahklrxrpfjoi

Impact of Parameter Variations on Circuits and Microarchitecture

Osman Unsal, James Tschanz, Keith Bowman, Vivek De, Xavier Vera, Antonio Gonzalez, Oguz Ergin
2006 IEEE Micro  
His research interests include low-power digital circuits, design techniques, and methods for tolerating parameter variations.  ...  The leakage limit is a function of frequency; low-frequency dies have less switching power and thus can tolerate greater leakage for the same total power constraint.  ... 
doi:10.1109/mm.2006.122 fatcat:2qayw5i7nfegrbz7yzsv3caoa4

A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation

Maziar Goudarzi, Tohru Ishihara, Hiroto Yasuura
2007 2007 Asia and South Pacific Design Automation Conference  
We show that in SRAM cells this leakage depends on the cell value and propose a first software-based runtime technique that suppresses such abnormal leakages by storing safe values in the corresponding  ...  Analysis and experimental results on commercial processors confirm that the technique is viable if the standby duration is more than a small fraction of a second.  ...  This work is also supported by Core Research for Evolutional Science and Technology (CREST) project of Japan Science and Technology Corporation (JST). We are grateful for their support.  ... 
doi:10.1109/aspdac.2007.358100 dblp:conf/aspdac/GoudarziIY07 fatcat:giexcx6iijd4hchr7vm37uecjq

Process Variations and Process-Tolerant Design

Swarup Bhunia, Saibal Mukhopadhyay, Kaushik Roy
2007 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07)  
To deal with increasing parameter variations, it is important to accurately model the impact of device parameter variations at circuit level and develop process-tolerant design techniques for both logic  ...  This article analyzes the impact of process parameter variations on logic circuits and memory and focuses on some major works in the area of process-tolerant design methodology at circuiffarchitecture  ...  Section I1 presents some major techniques for process-tolerant logic design.  ... 
doi:10.1109/vlsid.2007.131 dblp:conf/vlsid/BhuniaMR07 fatcat:haw2cidqhng7ngucgvwiftnsza

Non-uniform Set-Associative Caches for Power-Aware Embedded Processors [chapter]

Seiichiro Fujii, Toshinori Sato
2004 Lecture Notes in Computer Science  
Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies.  ...  This paper proposes a simple technique to reduce the static energy due to subthreshold leakage current.  ...  While this technique is originally proposed for high-performance processors [4] , we adopt it for low-power embedded processors and we call our proposed cache non-uniform setassociative (NUSA) cache.  ... 
doi:10.1007/978-3-540-30121-9_21 fatcat:ydyrxj2wz5acfh4x7fdq6qktm4

A Survey of Architectural Techniques for Managing Process Variation

Sparsh Mittal
2016 ACM Computing Surveys  
The aim of this paper is to provide insights to the researchers into the state-of-art in PV management techniques and motivate them to further improve these techniques for designing PV resilient processors  ...  In this paper, we present a survey of architectural techniques for managing process variation (PV) in modern processors.  ...  Effect on processor design and performance .  ... 
doi:10.1145/2871167 fatcat:6isx7an56ze63jqnpbkuw5pdcm

Test consideration for nanometer-scale CMOS circuits

Kaushik Roy, T.M. Mak, K.-T. Cheng
2006 IEEE Design & Test of Computers  
We now consider a process-tolerant cache architecture suitable for high-performance memories to detect and replace faulty cells by adaptively resizing the cache.  ...  Moreover, existing leakage reduction techniques such as transistor stacking and multiple-threshold design can lose their effectiveness in aggressively scaled technologies. 1,2 With high intrinsic leakage  ... 
doi:10.1109/mdt.2006.52 fatcat:ichk4podpvh4diznseqjwup7ti

Keeper Designs for Wide Fan in Dynamic Logic

Sarthak Bhuva, Praneeta Kalsait
2016 International Journal of Microelectronics Engineering  
In this era, high performance and multifunctional modules to have in the modern microprocessors has become essential. Dynamic gates have been a brilliant choice in the design of these modules.  ...  rate sensing keeper & variation tolerant keeper design and discuss each design's limitation.  ...  Acknowledgements We would take this opportunity to thank God, Our Alma matter-VJTI for providing the necessary infrastructure for our research work.  ... 
doi:10.5121/ijme.2016.2101 fatcat:5ia36itqyvfa5cilnyk5b55zr4

Review and classification of gain cell eDRAM implementations

Adam Teman, Pascal Meinerzhagen, Andreas Burg, Alexander Fish
2012 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel  
Several industrial and academic publications have presented GC memory implementations for various target applications, including high-performance processor caches, wireless communication memories, and  ...  In this paper, we review and compare the recent publications, examining the design requirements and the implementation techniques that lead to achievement of the required design metrics of these applications  ...  High−end processors Wireless SoC TABLE I DRIVER I OPERATING MODES Category High Performance Processor Caches Publication [9,12,24] [11] [13] [5,22] [2,14] [3] Bitcell MW MR GD  ... 
doi:10.1109/eeei.2012.6377022 fatcat:wrf43obipzeklny4fpnmg5bvky

A leakage-energy-reduction technique for highly-associative caches in embedded systems

Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato
2004 SIGARCH Computer Architecture News  
Power consumption is becoming one of the most important constraints for microprocessor design in nanometerscale technologies.  ...  This paper proposes a simple technique to reduce the static energy.  ...  While this technique is originally proposed for high-performance processors [3] , we adopt it for low-power embedded processors and we call our proposed cache non-uniform set-associative (NUSA) cache.  ... 
doi:10.1145/1024295.1024302 fatcat:ptkdpz3m4beu3idzfhjrecroti
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