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An Optimization Method for Designing LDPC Analog Decoders Based on Frequent Subgraph Mining Algorithm
2016
International Journal of Signal Processing, Image Processing and Pattern Recognition
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To lower the mapping complexity of designing analog decoders, a method to optimize the design of low-density parity-check (LDPC) analog decoders is proposed in this paper. ...
Moreover, this method can extend to optimize the design of other analog decoders for linear block codes, such as BCH and RS codes. ...
In [6] , analog decoders for turbo-style and tail-biting trellis codes were proposed, which provided a different way for LDPC decoder implementation. ...
doi:10.14257/ijsip.2016.9.10.12
fatcat:37en453sxzazlixxweuezcz5ti
A Subthreshold PMOS Analog Cortex Decoder for the (8, 4, 4) Hamming Code
2009
ETRI Journal
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This generates a large number of hidden variables and increases the complexity of the scheduling and initialization. However, the structure of the encoder is well suited for analog decoding. ...
This paper presents a method for decoding high minimal distance (d min ) short codes, termed Cortex codes. ...
Fig. 3 and in Fig. 4(b) for the LDPC-like decoder and Cortex decoder, respectively. Considering the low number of analog inputs, we fed them in parallel to the decoders. ...
doi:10.4218/etrij.09.0109.0207
fatcat:gypldjgzwbdupavlbym25vhv5m
Field-programmable gate array implementation of low-density parity-check codes decoder and hardware testbed
2013
IEEE 2013 Tencon - Spring
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The design of the LDPC decoder is described. In addition, a description of the hardware components that covers the important parts of the system from RF to channel decoding is included. ...
Furthermore, the results for the architectural complexity and performance in terms of the bit error rates over the testbed show that the proposed flexible design for IEEE 802.16e exhibits potential under ...
ACKNOWLEDGMENT The authors would like to express gratitude towards the Sirindhorn International Thai-German Graduate School of Engineering (TGGS), Bangkok, Thailand for their equipment supports. ...
doi:10.1109/tenconspring.2013.6584426
fatcat:imicyevk2nfyfjtsi53fy2qpdu
Power Reduction Techniques for LDPC Decoders
2008
IEEE Journal of Solid-State Circuits
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This paper investigates VLSI architectures for lowdensity parity-check (LDPC) decoders amenable to low-voltage and low-power operation. ...
To demonstrate the applicability of the proposed architecture for longer codes, we also report on a bit-serial fully-parallel decoder for the (2048, 1723) LDPC code in 10GBase-T standard synthesized with ...
ACKNOWLEDGMENT The authors would like to thank the editors and reviewers of IEEE TRANSACTIONS ON VLSI SYSTEMS for their valuable comments in the initial stages of this submission. ...
doi:10.1109/jssc.2008.925402
fatcat:snzpqiar6fbgrk7buivznwdzuy
Design and Development of an Improved Split Row Decoding Algorithm with Reduced BER
2014
Research Journal of Applied Sciences Engineering and Technology
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The usage of LDPC codes, especially in the error correction schemes, is tremendously increasing in the modern era. ...
In the conventional approach, the entire matrix which is computed always leads to computational complexity. As for this, the matrix is split into two equal halves and then error checking is done. ...
for a LDPC code in comparison to the Split-Row decoding algorithm. ...
doi:10.19026/rjaset.8.1103
fatcat:fpti3c2eefguje575xzb7at64a
Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations
2019
IEEE Communications Surveys and Tutorials
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We show that the overall implementation complexity of turbo, LDPC and polar decoders depends on numerous other factors beyond their computational complexity. ...
the LDPC code family for enhanced Mobile Broad Band (eMBB) data and polar codes for eMBB control. ...
Parameter
Turbo decoder
LDPC Decoder
Polar Decoder
Computational complexity
Higher for most coding rates.
Low at low coding rates
Lower for most coding rates. ...
doi:10.1109/comst.2019.2893851
fatcat:rv2p4a4ol5c2dneveopxsxwqqq
Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design
2013
IEEE Transactions on Very Large Scale Integration (vlsi) Systems
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Kaminska, "Oscillation-based test strategy for analog and mixed-signal integrated circuits," indard 1500 compatible oscillation ring test methodology for interconnect delay and crosstalk detection," ...
Sakaguchi, "Oscillation fault diagnosis for analog circuits based on boundary search with perturbation model," in Proc. Int. Symp. Circuits Syst., 1994, pp. 93-96. [2] K. Arabi and B. ...
The proposed decoder architecture based on BC-RS-LDPC codes has a high data throughput of 41 Gb/s and low hardware complexity. ...
doi:10.1109/tvlsi.2012.2210452
fatcat:rbpxkut775eqxndv5whjs4voxu
BER Performance Analysis of a Concatenated Low Density Parity Check Encoded OFDM System in AWGN and Fading Channels
2009
Journal of Scientific Research
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In this paper, we investigate the bit error rate (BER) performance of a concatenated low density parity check (LDPC) encoded orthogonal frequency-division multiplexing (OFDM) system on color image transmission ...
The transmitted color image is found to have retrieved effectively under noisy and fading situations with implementation of sum-product algorithm, an effective iterative based LDPC decoding scheme. ...
LDPC codes are linear block codes showing good block error correcting capability and linear decoding complexity in time. ...
doi:10.3329/jsr.v2i1.2724
fatcat:amf7bjbn4zb3rkdb5z2whzolwq
Challenges and some new directions in channel coding
[article]
2015
arXiv
pre-print
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Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: spatially coupled Low-Density Parity-Check (LDPC) codes, non-binary LDPC codes, and polar ...
coding. ...
In this section, we will discuss research advances in low complexity decoding and also present a class of LDPC codes with an associated novel decoding algorithm known as Analog Digital Belief Propagation ...
arXiv:1504.03916v1
fatcat:3bfjceo2kbbovb7rk2hw3jwudu
Iterative decoder architectures
2003
IEEE Communications Magazine
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IMPACT OF CODE CONSTRUCTION ON DECODER ARCHITECTURES The desire for large SNR gains frequently conflicts with the requirements for low complexity and high flexibility of the decoder. ...
Implementation was optimized for
low power. 500 Mb/s high throughput
MAP decoder is theoretically feasible
Custom ASIC (Analog) Parallel
Analog MAP decoder in BiCMOS
Interleavers not included. ...
doi:10.1109/mcom.2003.1222729
fatcat:aqa7i42rojfxhdtau3tony3cqq
Ultra-Low-Power Error Correction Circuits: Technology Scaling and Sub-$V_{ \rm T}$ Operation
2012
IEEE Transactions on Circuits and Systems - II - Express Briefs
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Index Terms-Analog decoders, biomedical implants, error correction codes (ECC), sub-threshold, ultra-low voltage. ...
Sub-V T implementation is predicted to offer 29× gain in power consumption for a (3,6) low-density parity-check decoder of length N = 512 operating at a throughput of 200 Mb/s, compared to standard digital ...
These methods were first reported by Gallager for decoding LDPC codes with sparse parity-check matrices and large N . ...
doi:10.1109/tcsii.2012.2231040
fatcat:xywl3dnpizbt7lyno4rhpbofeq
FPGA Implementation of Decoder Architectures for High Throughput Irregular LDPC Codes
2016
Indian Journal of Science and Technology
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Objective: VLSI implementation of Decoder Architecture for high throughput using LDPC codes. ...
LDPC codes are well-known linear block codes. The computational complexity of LDPC codes is very high as compared to other existing codes like Convolutional codes and Turbo codes. ...
FPGA implementation LDPC decoder on Virtex FPGA was proposed which focuses on low complexity and high speed 9 . ...
doi:10.17485/ijst/2016/v9i48/97269
fatcat:57fxhee65rfmjfkr2goresfcvi
Challenges and some new directions in channel coding
2015
Journal of Communications and Networks
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Three areas of ongoing research in channel coding are surveyed, and recent developments are presented in each area: spatially coupled Low-Density Parity-Check (LDPC) codes, nonbinary LDPC codes, and polar ...
coding. ...
1 Apologies to mechanics researchers for the seemingly disparaging remark. ...
doi:10.1109/jcn.2015.000063
fatcat:dy55a6swijfhxkcq2urpgyth6y
Progressive Coding and Iterative Source-Channel Decoding in Wireless Data Gathering Networks
2011
2011 IEEE Global Telecommunications Conference - GLOBECOM 2011
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Here we compare the performance of two codes with low decoding complexity, Repeat-Accumulate (RA) and Low-Density Parity-Check (LDPC) codes, in combination with two progressive coding schemes. ...
Results show that progressive coding performs better than non-progressive coding, and RA codes perform better with lower computational complexity than LDPC codes, both for channeldecoding-only and iterative ...
The relative complexity of source-channel decoding with RA codes compared to that with LDPC codes is the same as the relative complexity for channel decoding alone, showing a complexity savings with RA ...
doi:10.1109/glocom.2011.6133958
dblp:conf/globecom/LiFH11
fatcat:sngg4o2p2jgj5einsko4usotoi
Low-density parity check codes for long-haul optical communication systems
2002
IEEE Photonics Technology Letters
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Foward error correction (FEC) scheme based on low density parity check codes (LDPC) codes is presented in this paper. ...
Index Terms-Forward error correction, long-haul transmission, low-density parity check codes, optical communications. ...
Error performance and decoder hardware complexity can be further improved by using another type of iteratively decodable coding schemes, in particular low-density parity check codes. ...
doi:10.1109/lpt.2002.1022020
fatcat:bxrhz5vzs5bclpyemisi4miqwy
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