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Kernel-Kernel communication in a shared-memory multiprocessor

Eliseu M. Chaves, Prakash Ch. Das, Thomas J. Leblanc, Brian D. Marsh, Michael L. Scott
1993 Concurrency Practice and Experience  
Either approach to interkernel communication can be used in a large-scale shared-memory multiprocessor.  ...  In the standard kernel organization on a bus-based multiprocessor, all processors share the code and data of the operating system; explicit synchronization is used to control access to kernel data structures  ...  CDA-8822724, a DmPA/NASA Graduate Research Assistantship in Parallel Processing, the Federal University of Rio de Janeiro, and the Brazilian National Research Council.  ... 
doi:10.1002/cpe.4330050302 fatcat:4w3r3cwshjbbpdxp2ivchj2dpq

Page 62 of Journal of Research and Practice in Information Technology Vol. 20, Issue 2 [page]

1988 Journal of Research and Practice in Information Technology  
However, in a closely-coupled multiprocessor system, the inter-kernel communication becomes more complex.  ...  A Distributed Operating System Kernel for a Closely-Coupled Multiprocessor Kernel Communications (/KC) protocol, for communica- tion between kernels running on separate nodes.  ... 

User-level interprocess communication for shared memory multiprocessors

Brian N. Bershad, Thomas E. Anderson, Edward D. Lazowska, Henry M. Levy
1991 ACM Transactions on Computer Systems  
Interprocess communication (IPC), in particular IPC oriented towards local cornmzmzcation  ...  On a shared memory multiprocessor, these problems have a solution: eliminate the kernel from the path of cross-address space communication.  ...  In contrast to URPC, contemporary uniprocessor kernel structures are not well suited for use on shared memory multiprocessors: -Kernel-level communication and thread management facilities  ... 
doi:10.1145/103720.114701 fatcat:ggfdn35vuzflvknsq73g2lu54e

The duality of memory and communication in the implementation of a multiprocessor operating system

M. Young, A. Tevanian, R. Rashid, D. Golub, J. Eppinger
1987 ACM SIGOPS Operating Systems Review  
All threads within a task share the address space and capabilities of that task. Inter-Process Communication Inter-process communication (IPC) in Mach is defined in terms of ports and messages.  ...  Its history led to a design that provided both the message passing prevalent in Accent and new support for parallel processing and shared memory.  ...  The second release of Mach was made in April, 1987. The next release is scheduled for the end of October, 1987.  ... 
doi:10.1145/37499.37507 fatcat:j7vt2rv2zzdmxjrc7yxhl6um5u

The duality of memory and communication in the implementation of a multiprocessor operating system

M. Young, A. Tevanian, R. Rashid, D. Golub, J. Eppinger
1987 Proceedings of the eleventh ACM Symposium on Operating systems principles - SOSP '87  
All threads within a task share the address space and capabilities of that task. Inter-Process Communication Inter-process communication (IPC) in Mach is defined in terms of ports and messages.  ...  Its history led to a design that provided both the message passing prevalent in Accent and new support for parallel processing and shared memory.  ...  The second release of Mach was made in April, 1987. The next release is scheduled for the end of October, 1987.  ... 
doi:10.1145/41457.37507 dblp:conf/sosp/YoungTRGECBBB87 fatcat:7mblbcll75afdphha3jieb22ti

On the Robust Mapping of Dynamic Programming onto a Graphics Processing Unit

Shucai Xiao, Ashwin M. Aji, Wu-chun Feng
2009 2009 15th International Conference on Parallel and Distributed Systems  
the multiprocessors of a GPU, which could easily cripple performance as communication between multiprocessors is not natively supported in a GPU.  ...  However, the fundamental issue with such ensemble runs is that the problem size to achieve this speed-up is limited to the available shared memory and cache of a GPU multiprocessor.  ...  This work was supported in part by an IBM Faculty Award and a NVIDIA Professor Partnership Award.  ... 
doi:10.1109/icpads.2009.110 dblp:conf/icpads/XiaoAF09 fatcat:i7feinjdkncalglj667eew3zba

Mach: A system software kernel

R.F. Rashid, H. Tokuda
1990 Computing Systems in Engineering  
Key elements of the Mach design support facilities such as System V streams, 4.2BSD sockets, which allow it to efficiently support system software include pty's, various forms of semaphores, shared memory  ...  needs and technology, Unix has been modified to provide a staggering number of different mechanisms for managing ob-The Mach operating system can be used as a system software kernel which can support a  ...  Mach threads and interprocess communication Transparent Shared Libraries A thread in Mach is a CPU flow of control executing within Mach provides the notion of a transparent shared library.  ... 
doi:10.1016/0956-0521(90)90004-5 fatcat:vsz5p3l33rdobka3zysmcoeob4

Implementation Issues for the Psyche Multiprocessor Operating System

Michael L. Scott, Thomas J. LeBlanc, Brian D. Marsh, Timothy G. Becker, Cezary Dubnicki, Evangelos P. Markatos, Neil G. Smithline
1989 Computing Systems  
In addition, the Psyche development effort is addressing a host of implementation issues for large-scale shared-memory multiprocessors, including the organization of kernel functions, data structures,  ...  Winter 1990 101 multiprocessor, though many of the issues we consider apply to any operating system kernel on a large-scale shared-memory machine.  ...  Sean Colbath, Yenjo Han, Kurt Jones, John Iaeadley, Dave Tilley, and Jack Veenstra have helped build kernel or user-level software. Bill Bolosþ contributed to earþ design discussions.  ... 
dblp:journals/csys/ScottLMBDMS89 fatcat:bh4nmmw3r5eqhg2vkizzdxs42e

Cache memory behavior of advanced PDE solvers [chapter]

D. Wallin, H. Johansson, S. Holmgren
2004 Advances in Parallel Computing  
Three different partial differential equation (PDE) solver kernels are analyzed in respect to cache memory performance on a simulated shared memory computer.  ...  Unfortunately, such prefetchers often lead to additional address snoops in multiprocessor caches.  ...  We also would like to express gratitude to Markus Nordén for the CFD kernel and to Henrik Löf for the CEM kernel modeled in this paper.  ... 
doi:10.1016/s0927-5452(04)80061-3 fatcat:me22hdu4xbc5pojhrg5zs7dcxa

The impact of architectural trends on operating system performance

M. Rosenblum, E. Bugnion, S. A. Herrod, E. Witchel, A. Gupta
1995 Proceedings of the fifteenth ACM symposium on Operating systems principles - SOSP '95  
The paper presents a detailed decomposition of execution time (e.g., instruction execution time, memory stall time separately for instructions and data, synchronization time) for important kernel services  ...  A large fraction of the stalls are due to coherence misses caused by communication between processors.  ...  Anoop Gupta is partially supported by a National Science Foundation Presidential Young Investigator award.  ... 
doi:10.1145/224056.224078 dblp:conf/sosp/RosenblumBHWG95 fatcat:2comfp7ppvcrpage2i5ay4y7oy

The impact of architectural trends on operating system performance

M. Rosenblum, E. Bugnion, S. A. Herrod, E. Witchel, A. Gupta
1995 ACM SIGOPS Operating Systems Review  
The paper presents a detailed decomposition of execution time (e.g., instruction execution time, memory stall time separately for instructions and data, synchronization time) for important kernel services  ...  A large fraction of the stalls are due to coherence misses caused by communication between processors.  ...  Anoop Gupta is partially supported by a National Science Foundation Presidential Young Investigator award.  ... 
doi:10.1145/224057.224078 fatcat:56e3x7q6bvevdgxgvpuznchfba

Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures

R. Rashid, A. Tevanian, M. Young, D. Golub, R. Baron, D. Black, W.J. Bolosky, J. Chew
1988 IEEE transactions on computers  
This paper describes the design and implementation of virtual memory management within the CMU Mach Operating System and the experiences gained by the Mach kernel group in porting that system to a variety  ...  Although these systems vary considerably in the kind of hardware support for memory management they provide, the machine-dependent portion of Mach virtual memory consists of a single code module and its  ...  In addition to differences in address translation hardware, existing multiprocessors differ in the kinds of shared memory access they make available to individual CPUs.  ... 
doi:10.1109/12.2242 fatcat:5ccs6edc4namtohwne72li5v7a

Efficient Mapping of Streaming Applications for Image Processing on Graphics Cards [chapter]

Richard Membarth, Hritam Dutta, Frank Hannig, Jürgen Teich
2019 Advances in Biochemical Engineering/Biotechnology  
Double Buffering Support application mapping final application double buffering support (device driver) communication support computation kernel communication support computation kernel application  ...  For deployment in a streaming application with steadily new incoming data, it is shown that the memory transfer overhead to the graphics card is reduced by a factor of six using double buffering.  ...  In addition 16384 registers and 16384 bytes of on-chip shared memory are provided to all threads executed simultaneously on one multiprocessor.  ... 
doi:10.1007/978-3-662-58834-5_1 fatcat:tz3azu6gb5hj5mysy2whv7grui

Fast circuit simulation on graphics processing units

Kanupriya Gulati, John F. Croix, Sunil P. Khatri, Rahm Shastry
2009 2009 Asia and South Pacific Design Automation Conference  
SPICE based circuit simulation is a traditional workhorse in the VLSI design process. Given the pivotal role of SPICE in the IC design flow, there has been significant interest in accelerating SPICE.  ...  Since a large fraction (on average 75%) of the SPICE runtime is spent in evaluating transistor model equations, a significant speedup can be availed if these evaluations are accelerated.  ...  The total number of registers per multiprocessor is 8192. • A shared memory that is shared by all the processors of a multiprocessor.  ... 
doi:10.1109/aspdac.2009.4796514 dblp:conf/aspdac/GulatiCKS09 fatcat:jqgxl3ohljgq7lewfdj3zn4qeq

A Fast GPU Implementation for Solving Sparse Ill-Posed Linear Equation Systems [chapter]

Florian Stock, Andreas Koch
2010 Lecture Notes in Computer Science  
In this paper we will present a GPU-accelerated scheme for a Conjugate Gradient (CG) solver, with focus on the SpMV.  ...  Image reconstruction, a very compute-intense process in general, can often be reduced to large linear equation systems represented as sparse under-determined matrices.  ...  Note that the threads within a block may communicate quickly via the shared memory and can be efficiently synchronized.  ... 
doi:10.1007/978-3-642-14390-8_48 fatcat:4ybhuquhhre43gshr5tvpub7iq
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