107 Hits in 0.93 sec

Chique en sjofel moeten naast elkaar kunnen werken: De Amsterdamse projectleider broedplaatsenbeleid Van Straten over Het Experiment

Jeroen Van der Velden
2001 Agora  
JEROEN VAN DER VELDEN Broedplaats aan aan de Plantage Doklaan in Amsterdam. (Foto jeroen van der Ve/den) Wat houdt het broedplaatsenbeleid in Amsterdam in? < ( G De De Kl' Al D€ t.n  ...  Wat zijn de belangen van de verschillende partijen? Vraaggesprek met projectleider jeroen van Straaten over sociale werkruimtes en de paradox van het broedplaatsenbeleid.  ...  (Foto jeroen van der Ve/den) 'Ja, je zou het kunnen verbreden.  ... 
doi:10.21825/agora.v17i5.9329 fatcat:xbta4oclunagdiouiopok7ppkm

Hyperelliptic integrals and generalized arithmetic–geometric mean

Jeroen Spandaw, Duco van Straten
2012 The Ramanujan journal  
We show how certain determinants of hyperelliptic periods can be computed using a generalized arithmetic-geometric mean iteration, whose initialisation parameters depend only on the position of the ramification points. Special attention is paid to the explicit form of this dependence and the signs occurring in the real domain.
doi:10.1007/s11139-011-9353-7 fatcat:xrbphzt6inbejkwzthrxgjfj5y

Exploring ILP and TLP on a Polymorphic VLIW Processor [chapter]

Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Stephan Wong
2017 Lecture Notes in Computer Science  
In today's computing environments, the concurrent execution of multiple applications/threads is common and multi-cores are very well-suited to handle such workloads. However, they suffer from the fact that any mismatch between the application's inherent instruction-level parallelism (ILP) and the core's parallelism leads to unused resources or loss in performance. An accepted solution is to include several types of cores and match them dynamically depending on the performance needs of the
more » ... ation. This approach becomes less efficient when the number of cores does not match the number of parallel threads. Furthermore, the heterogeneity of (fixed) cores cannot be increased indefinitely as it would result in even higher degrees of mismatching and increased movement of instruction and data streams. In this paper, we are proposing a polymorphic processor, based on VLIW architectures, that can adapt its issue-width during runtime. By design, the processor can be perceived as a single wide core (8-issue VLIW) or two medium-wide cores (4-issue) or four small cores (2-issue) that can run high-ILP/low DLP, medium-ILP/medium DLP, and low-ILP/high-DLP applications, respectively. Furthermore, we are executing one single generic binary while performing these reconfigurations. In order to show the effectiveness of our approach, we synthesized different versions of the core to represent fixed heterogeneous cores and compared them to the dynamic implementation of the core. Our experiments show that the dynamically adaptive solution performs on average 7% faster and uses 5% less area than a platform which consists of fixed cores with 1.5× as many datapaths.
doi:10.1007/978-3-319-54999-6_14 fatcat:3o7imcvjfngkfcalai767u3pze

Tydi: an open specification for complex data structures over hardware streams

Johannus Willem Peltenburg, Matthijs Brobbel, Jeroen Van Straten, Zaid Al-Ars, Peter Hofstee
2020 IEEE Micro  
Jeroen van Straten is a research engineer at the Quantum & Computer Engineering department of the Tu Delft. Jeroen works on tools for quantum simulators and digital circuit design.  ... 
doi:10.1109/mm.2020.2996373 fatcat:iyngd63uqvfjbcejgmpe3breee

Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications

Joost Hoozemans, Rob de Jong, Steven van der Vlugt, Jeroen Van Straten, Uttam Kumar Elango, Zaid Al-Ars
2019 Journal of Signal Processing Systems  
This paper presents and evaluates an approach to deploy image and video processing pipelines that are developed frame-oriented on a hardware platform that is stream-oriented, such as an FPGA. First, this calls for a specialized streaming memory hierarchy and accompanying software framework that transparently moves image segments between stages in the image processing pipeline. Second, we use softcore VLIW processors, that are targetable by a C compiler and have hardware debugging capabilities,
more » ... o evaluate and debug the software before moving to a High-Level Synthesis flow. The algorithm development phase, including debugging and optimizing on the target platform, is often a very time consuming step in the development of a new product. Our proposed platform allows both software developers and hardware designers to test iterations in a matter of seconds (compilation time) instead of hours (synthesis or circuit simulation time).
doi:10.1007/s11265-018-1422-3 pmid:30873259 pmcid:PMC6390719 fatcat:cmnzbsesdvhwbkqgf46bpdb4my

Combined Internet-Based Cognitive-Behavioral and Chronobiological Intervention for Insomnia: A Randomized Controlled Trial

Kim Dekker, Jeroen S. Benjamins, Teodora Maksimovic, Marco Filardi, Winni F. Hofman, Annemieke van Straten, Eus J.W. Van Someren
2019 Psychotherapy and Psychosomatics  
.; Van Someren, E.J.W.  ... 
doi:10.1159/000503570 pmid:31639813 pmcid:PMC7158227 fatcat:2f2jdvudxfdc7jgvbnscu4laxa

Multiple contexts in a multi-ported VLIW register file implementation

Joost Hoozemans, Jens Johansen, Jeroen Van Straten, Anthony Brandon, Stephan Wong
2015 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)  
The register file is an expensive component in the design of any processor, especially, when considering the additional ports that are needed to support multiple datapaths within a wide-issue VLIW processor. In a recent work, these additional resources were used to dynamically reconfigure the register file to support a dynamically reconfigurable VLIW core. The design can be perceived as a single 8-issue, two 4-issue, or four 2-issue VLIW cores. Consequently, the multi-ported design can operate
more » ... n different modes, namely as one, two, or f our register files, respectively, corresponding to the active number of cores. The implementation of the register file design on FPGAs using Block RAMs still results in unused resources due to the coarseness of the Block RAMs. In this paper, we propose to re-purpose these unused BRAM resources to additionally support multiple contexts next to earliermentioned modes. In this manner, the 8-issue, 4-issue, and 2issue cores have access to 4, 2, and 1 contexts, respectively. Consequently, we can avoid saving and restoring of the task states in a multi-task environment, turning context switching from a traditionally time-consuming event to an almost instantaneous event. The advantage of this is the reduction of interrupt latency and task switching latency, which are important in real-time and embedded systems. Our results show that our technique can improve interrupt latency by a factor of 17.4× compared to using a software register spill routine, depending on the behavior of the memory system. Likewise, the task switching time can be improved by 6.7×.
doi:10.1109/reconfig.2015.7393329 dblp:conf/reconfig/HoozemansJSBW15 fatcat:z2knylrv3fgkfmu6pfwdkb6hmy

High-Q integrated RF passives and RF-MEMS on silicon

Joost T.M. van Beek, Marc H.W.M. van Delden, Auke van Dijken, Patrick van Eerd, Andre B.M. Jansman, Anton L.A.M. Kemmeren, Theo G.S.M. Rijks, Peter G. Steeneken, Jaap den Toonder, Mathieu J.E. Ulenaers, Arnold den Dekker, Pieter Lok (+5 others)
2003 Materials Research Society Symposium Proceedings  
A technology platform is described for the integration of low-loss inductors, capacitors, and MEMS capacitors on a high-resistivity Si substrate. Using this platform the board space area taken up by e.g. a DCS PA output impedance matching circuit can be reduced by 50%. The losses of passive components that are induced by the semi-conducting Si substrate can effectively be suppressed using a combination of surface amorphisation and the use of poly crystalline Si substrates. A MEM switchable
more » ... itor with a capacitance switching factor of 40 and an actuation voltage of 5V is demonstrated. A continuous tuneable dual-gap capacitor is demonstrated with a tuning ratio of 9 using actuation voltages below 15V.
doi:10.1557/proc-783-b3.1 fatcat:y6fyvkbnvbggdcfsrw6fa3gvoe

ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

Joost Hoozemans, Jeroen van Straten, Timo Viitanen, Aleksi Tervo, Jiri Kadlec, Zaid Al-Ars
2019 Journal of Signal Processing Systems  
Delft University of Technology, Delft, The Netherlands Zaid Al-Ars Joost Hoozemans Jeroen van Straten Timo Viitanen viitanet  ... 
doi:10.1007/s11265-018-1424-1 pmid:30873260 pmcid:PMC6390713 fatcat:7fnj3sap6je47gwlihk6hb5wxq

Effectiveness of internet-supported cognitive behavioral and chronobiological interventions and effect moderation by insomnia subtype: study protocol of a randomized controlled trial

Kim Dekker, Jeroen S. Benjamins, Annemieke Van Straten, Winni F. Hofman, Eus J. W. Van Someren
2015 Trials  
.; Benjamins, J.S; van Straten, A.; Hofman, W.F.; van Someren, E.J.W. .  ... 
doi:10.1186/s13063-015-0790-2 pmid:26141682 pmcid:PMC4490722 fatcat:htnzg5fvfncs5nrvslmqbxov7a

Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow

Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel, Zaid Al-Ars, H. Peter Hofstee
2021 Journal of Signal Processing Systems  
AbstractAs big data analytics systems are squeezing out the last bits of performance of CPUs and GPUs, the next near-term and widely available alternative industry is considering for higher performance in the data center and cloud is the FPGA accelerator. We discuss several challenges a developer has to face when designing and integrating FPGA accelerators for big data analytics pipelines. On the software side, we observe complex run-time systems, hardware-unfriendly in-memory layouts of data
more » ... ts, and (de)serialization overhead. On the hardware side, we observe a relative lack of platform-agnostic open-source tooling, a high design effort for data structure-specific interfaces, and a high design effort for infrastructure. The open source Fletcher framework addresses these challenges. It is built on top of Apache Arrow, which provides a common, hardware-friendly in-memory format to allow zero-copy communication of large tabular data, preventing (de)serialization overhead. Fletcher adds FPGA accelerators to the list of over eleven supported software languages. To deal with the hardware challenges, we present Arrow-specific components, providing easy-to-use, high-performance interfaces to accelerated kernels. The components are combined based on a generic architecture that is specialized according to the application through an extensive infrastructure generation framework that is presented in this article. All generated hardware is vendor-agnostic, and software drivers add a platform-agnostic layer, allowing users to create portable implementations.
doi:10.1007/s11265-021-01650-6 fatcat:5ranxhrntjcrtd77opsaz2e7da

A sparse VLIW instruction encoding scheme compatible with generic binaries

Anthony Brandon, Joost Hoozemans, Jeroen van Straten, Arthur Lorenzon, Anderson Sartor, Antonio Carlos Schneider Beck, Stephan Wong
2015 2015 International Conference on ReConFigurable Computing and FPGAs (ReConFig)  
Very Long Instruction Word (VLIW) processors are commonplace in embedded systems due to their inherent lowpower consumption as the instruction scheduling is performed by the compiler instead by sophisticated and power-hungry hardware instruction schedulers used in their RISC counterparts. This is achieved by maximizing resource utilization by only targeting a certain application domain. However, when the inherent application ILP (instruction-level parallelism) is low, resources are
more » ... d/wasted and the encoding of NOPs results in large code sizes and consequently additional pressure on the memory subsystem to store these NOPs. To address the resource-utilization issue, we proposed a dynamic VLIW processor design that can merge unused resources to form additional cores to execute more threads. Therefore, the formation of cores can result in issue widths of 2, 4, and 8. Without sacrificing the possibility of code interruptability and resumption, we proposed a generic binary scheme that allows a single binary to be executed on these different issue-width cores. However, the code size issue remains as the generic binary scheme even slightly further increases the number NOPS. Therefore, in this paper, we propose to apply a well-known stop-bit code compression technique to the generic binaries that, most importantly, maintains its code compatibility characteristic allowing it to be executed on different cores. In addition, we present the hardware designs to support this technique in our dynamic core. For prototyping purposes, we implemented our design on a Xilinx Virtex-6 FPGA device and executed 14 embedded benchmarks. For comparison, we selected a nondynamic/static VLIW core that incorporates a similar stop-bit technique for its code compression. We demonstrate, while maintaining code compatibility on top of a flexible dynamic VLIW processor, that the code size can be significantly reduced (up to 80%) resulting in energy savings, and that the performance can be increased (up to a factor of three). Finally, our experimental results show that we can use smaller caches (2 to 4 times as small), which will further help in decreasing energy consumption.
doi:10.1109/reconfig.2015.7393361 dblp:conf/reconfig/BrandonHSLSBW15 fatcat:zihbux5tejepbpgcrqarfwhkmy

Anti-SARS-CoV-2 IgG from severely ill COVID-19 patients promotes macrophage hyper-inflammatory responses [article]

Willianne Hoepel, Hung-Jen Chen, Sona Allahverdiyeva, Xue Manz, Jurjan Aman, Peter Bonta, Philip Brouwer, Steven de Taeye, Tom Caniels, Karlijn van der Straten, Korneliusz Golebski, Guillermo Griffith (+17 others)
2020 bioRxiv   pre-print
For yet unknown reasons, severely ill COVID-19 patients often become critically ill around the time of activation of adaptive immunity. Here, we show that anti-Spike IgG from serum of severely ill COVID-19 patients induces a hyper-inflammatory response by human macrophages, which subsequently breaks pulmonary endothelial barrier integrity and induces microvascular thrombosis. The excessive inflammatory capacity of this anti-Spike IgG is related to glycosylation changes in the IgG Fc tail.
more » ... er, the hyper-inflammatory response induced by anti-Spike IgG can be specifically counteracted in vitro by use of the active component of fostamatinib, an FDA- and EMA-approved therapeutic small molecule inhibitor of Syk.
doi:10.1101/2020.07.13.190140 fatcat:otworc7fifh7bm6sqe5pqqv7zu

High titers and low fucosylation of early human anti-SARS-CoV-2 IgG promote inflammation by alveolar macrophages

Willianne Hoepel, Hung-Jen Chen, Chiara E. Geyer, Sona Allahverdiyeva, Xue D. Manz, Steven W. de Taeye, Jurjan Aman, Lynn Mes, Maurice Steenhuis, Guillermo R. Griffith, Peter I. Bonta, Philip J.M. Brouwer (+24 others)
2021 Science Translational Medicine  
We thank all the people involved, but particularly Diederik van de Beek, who initiated this biobank. Funding:  ... 
doi:10.1126/scitranslmed.abf8654 pmid:33979301 fatcat:rjaryfeo65f6zdjkabu3vqrko4

Do guided internet-based interventions result in clinically relevant changes for patients with depression? An individual participant data meta-analysis

Eirini Karyotaki, David Daniel Ebert, Liesje Donkin, Heleen Riper, Jos Twisk, Simone Burger, Alexander Rozental, Alfred Lange, Alishia D. Williams, Anna Carlotta Zarski, Anna Geraedts, Annemieke van Straten (+36 others)
2018 Clinical Psychology Review  
Psychological treatments have been shown to be effective in the treatment of depression Cuijpers, van Straten, Andersson, & van Oppen, 2008a) .  ...  Straten, Warmerdam, & Andersson, 2008b) .  ... 
doi:10.1016/j.cpr.2018.06.007 pmid:29940401 fatcat:gvs7glgkznbmnb6motbeov45xe
« Previous Showing results 1 — 15 out of 107 results