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Janus: An FPGA-Based System for High-Performance Scientific Computing

F. Belletti, M. Cotallo, A. Cruz, L.A. Fernandez, A. Gordillo-Guerrero, M. Guidetti, A. Maiorano, F. Mantovani, E. Marinari, V. Martin-Mayor, A. Muoz-Sudupe, D. Navarro (+11 others)
2009 Computing in science & engineering (Print)  
This paper describes JANUS, a modular massively parallel and reconfigurable FPGA-based computing system. Each JANUS module has a computational core and a host.  ...  The computational core is a 4x4 array of FPGA-based processing elements with nearest-neighbor data links.  ...  Sialino for their outstanding support during the commissioning of the first JANUS system.  ... 
doi:10.1109/mcse.2009.11 fatcat:uy6fojv45jcslf5pkgjzzoikmq

Janus II: A new generation application-driven computer for spin-system simulations

M. Baity-Jesi, R.A. Baños, A. Cruz, L.A. Fernandez, J.M. Gil-Narvion, A. Gordillo-Guerrero, D. Iñiguez, A. Maiorano, F. Mantovani, E. Marinari, V. Martin-Mayor, J. Monforte-Garcia (+12 others)
2014 Computer Physics Communications  
This domain of computational physics is a recognized grand challenge of high-performance computing: the resources necessary to study in detail theoretical models that can make contact with experimental  ...  This paper describes the architecture, the development and the implementation of Janus II, a new generation application-driven number cruncher optimized for Monte Carlo simulations of spin systems (mainly  ...  In particular we thank Pietro Lazzeri, Pamela Pedrini, Roberto Preatoni, Luigi Trombetta and Alessandro Zambardi for their professional and enthusiastic work. The Janus II project was supported by the  ... 
doi:10.1016/j.cpc.2013.10.019 fatcat:lwy6lvtq6ve5vmhhz5sxerup4i

Keynotes

Rainer Leupers, Raffaele Tripiccione, Henk Corporaal
2012 2012 IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors  
Due to power and performance reasons, MPSoC architectures are getting widespread in virtually all domains of computing.  ...  The amount of mobile data traffic is expected to grow by 1000x within the next decade, resulting in very high performance requirements.  ...  and cyber-physical systems, often require high computational performance.  ... 
doi:10.1109/asap.2012.38 fatcat:sodweh357baoxn4723rl6hliri

FPGA based technical solutions for high throughput data processing and encryption for 5G communication: A review

P. Visconti, R. Velazquez, Carolina Del-Valle Soto, R. de Fazio
2021 TELKOMNIKA (Telecommunication Computing Electronics and Control)  
In this review paper, at first, an overview of the key applications of FPGA-based platforms in 5G networks/systems is presented, exploiting the improved performances offered by such devices.  ...  FPGA-based implementations of cloud radio access network (C-RAN) accelerators, network function virtualization (NFV)-based network slicers, cognitive radio systems, and multiple input multiple output (  ...  Shen et al. presented an FPGA-based service gateway user plane (SGW-U) system in mobile edge computing (MEC) aimed to 5G scenario [62] .  ... 
doi:10.12928/telkomnika.v19i4.18400 fatcat:r6zybornqjal7p63o3ct7utkyi

Editorial

M. Weigel, A. Arnold, P. Virnau
2012 The European Physical Journal Special Topics  
a series GRAPE of special-purpose computers based on field-programmable gate arrays (FPGAs) has played a significant a  ...  Moore's law, predicting a doubling of the computational power of typical hardware about every two years, has successfully described the capabilities of single CPU systems for more than forty years.  ...  High-performance computing.  ... 
doi:10.1140/epjst/e2012-01633-0 fatcat:kutoljli3fa5vhwylf2fszofsq

The "Chimera": An Off-The-Shelf CPU/GPGPU/FPGA Hybrid Computing Platform

Ra Inta, David J. Bowman, Susan M. Scott
2012 International Journal of Reconfigurable Computing  
Scientists, increasingly fighting for valuable resources on conventional high-performance computing (HPC) facilities—often with a limited customizable user environment—are increasingly looking to hardware  ...  We describe here a heterogeneous CPU/GPGPU/FPGA desktop computing system (the "Chimera"), built with commercial-off-the-shelf components.  ...  Inta is supported by an Australian Research Council "Discovery" project and D. J. Bowman is supported by an Australian Research Council "Super Science" Project.  ... 
doi:10.1155/2012/241439 fatcat:xnlqwah4yrgmpklcjgedkwikuu

Process Simulation of Complex Biochemical Pathways in Explicit 3D Space Enabled by Heterogeneous Computing Platform

Jie Li, Amin Salighehdar, Narayan Ganesan
2014 2014 IEEE International Parallel & Distributed Processing Symposium Workshops  
Finally, we present the new heterogeneous computing framework integrating a FPGA and GPU to accelerate the computation and obtain better performance over the use of any single platform.  ...  Hence, there is a strong need for new underlying simulation algorithms as well as need for newer computing platforms, systems and techniques.  ...  ACKNOWLEDGEMENTS The authors would like to thank the Xilinx University Program(XUP) and the NVIDIA-Professor partnership for their generous support and donation helpful in carrying out this research.  ... 
doi:10.1109/ipdpsw.2014.199 dblp:conf/ipps/LiSG14 fatcat:dlhayrnt6fhbla65wfggjxsapa

Autonomous Probabilistic Coprocessing with Petaflips per Second

Brian Sutton, Rafatul Faria, Lakshmi A. Ghantasala, Risi Jaiswal, Kerem Y. Camsari, Supriyo Datta
2020 IEEE Access  
In this paper we present a concrete design for a probabilistic (p-) computer based on a network of p-bits, robust classical entities fluctuating between -1 and +1, with probabilities that are controlled  ...  A key contribution of this paper is the focus on a hardware metric − flips per second− as a problem and substrate-independent figure-of-merit for an emerging class of hardware annealers known as Ising  ...  As shown in the table, the FPGA based 8K-spin ApC achieves an energy per flip that is similar to the Janus II sequenced FPGA implementation.  ... 
doi:10.1109/access.2020.3018682 fatcat:cjdt6ebo65fexlgiigv2bsrhza

A network-centric approach to space-restricted distributed processing

M.R. Fowler, E. Stipidis, F.H. Ali
2009 Microprocessors and microsystems  
A similar analysis is presented for DGEMM when utilising a possible, modular, per node FPGA enhancement.  ...  Analysis in terms of weight and volume is undertaken when compared to a reference PC system for the example application RC5.  ...  DGEMM space to performance Beowulf clusters provide a cost-efficient alternative to specially built super-computers in the field of high-performance computing.  ... 
doi:10.1016/j.micpro.2009.05.002 fatcat:wnrusp6nrvcohfqjljhfvte6u4

Università degli Studi di Ferrara DOTTORATO DI RICERCA IN MATEMATICA-INFORMATICA COORDINATORE PROF.SSA LUISA ZANGHIRATI JANUS: A RECONFIGURABLE SYSTEM FOR SCIENTIFIC COMPUTING DOTTORANDO TUTORE

Xxi° Ciclo, Dott Filippo, Tripiccione Raffaele, Manuela
unpublished
The FPGA High Performance Computing Alliance (FHPCA) [29] Both these projects give to the computer science community an ecient proof that recongurable computing can be used in order to obtain high performance  ...  By we also developing these libraries, in some sense we dene an interface between our FPGA-based system and a general purpose processorbased computer.  ... 
fatcat:fpoyeril5fa3jksdtsbn6croq4

Compact CMOS Camera Demonstrator (C3D) for Ukube-1

R. D. Harriss, A. D. Holland, S. J. Barber, S. Karout, R. Burgon, B. J. Dryer, N. J. Murray, D. J. Hall, P. H. Smith, T. Grieg, J. H. Tutt, J. Endicott (+7 others)
2011 UV/Optical/IR Space Telescopes and Instruments: Innovative Technologies and Concepts V  
collaboration with e2v technologies and XCAM Ltd, have been selected to fly an EO (Earth Observation) technology demonstrator and in-orbit radiation damage characterisation instrument on board the UK Space  ...  Scheduled for launch in December 2011, this 1 year low cost programme should not only provide valuable data and outreach opportunities but also help to prove flight heritage for future missions.  ...  There is an flash based configuration device for storing the FPGA firmware configuration. There is also flash memory storage for storing the mission software.  ... 
doi:10.1117/12.895986 fatcat:z5nid6eeorelvfmohvidaykgje

Nature of the Spin Glass Phase in Finite Dimensional (Ising) Spin Glasses [article]

J.J. Ruiz-Lorenzo
2020 arXiv   pre-print
We also introduce some rigorous results based on the concept of metastate.  ...  Spin glasses are the paradigm of complex systems. These materials present really slow dynamics. However, the nature of the spin glass phase in finite dimensional systems is still controversial.  ...  These discrete models allow the supercomputers to achieve their maximum performance. • For Ising models, Janus I is equivalent to 10000 PC. • High degree of parallelization inside the boards. • Janus allows  ... 
arXiv:2006.12930v1 fatcat:j5oegjgguzb55ad3evw3ga5d4m

Open Robotic Controllers

Üveges Róbert, Ďurovský František, Lindr David
2016 Acta Electrotechnica et Informatica  
For testing hardware the Janus robot was used, which is an anthropomorphic two-armed robot, with eight degrees of freedom in each arm, and a stereo vision system.  ...  used for a high dynamic pick and place handling system.  ... 
doi:10.15546/aeei-2016-0017 fatcat:cn3qnt735rfhncw3dgwch4s3j4

Mathematical model and implementation of rational processing

H. Mora, J. Mora-Pascual, J.M. García-Chamizo, M.T. Signes-Pont
2017 Journal of Computational and Applied Mathematics  
This paper reviews other specialized arithmetic units based on existing formats to show ways to make high precision computing.  ...  Finally, extensive evaluation of this operator is performed to prove its ability for exact processing.  ...  devices or solving high performance computing applications.  ... 
doi:10.1016/j.cam.2016.05.001 fatcat:6ukl6rh7xfcordnpthlfaqcaue

Multi-Gigabit Microwave and Millimeter-Wave Communications Research at CSIRO

Xiaojing Huang, Y. Jay Guo, Jian A. Zhang
2014 2014 14th International Symposium on Communications and Information Technologies (ISCIT)  
However, current commercially available wireless backhaul systems neither provide sufficiently high speed nor meet the requirements to achieve both high speed and long range at the same time with sufficiently  ...  low latency for targeted applications.  ...  Similar announcement has been made by MIMOtech that it has launched Starburst Janus, an ultra high capacity packet radio for last mile backhaul, which utilizes a 4x4 LOS MIMO yielding a spectral efficiency  ... 
doi:10.1109/iscit.2014.7011973 dblp:conf/iscit/HuangGZ14 fatcat:t7kppdzezfcx3h3zriqif5ocyi
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