Filters








47,872 Hits in 5.5 sec

Rediscovering Majority Logic in the Post-CMOS Era: A Perspective from In-Memory Computing

John Reuben
2020 Journal of Low Power Electronics and Applications  
In view of this, memristive logic families which can implement MAJORITY gate and NOT (to make it functionally complete) are to be favored for in-memory computing.  ...  In this review, the efficiency of majority logic is analyzed from the perspective of in-memory computing.  ...  Conflicts of Interest: The author declares no conflict of interest.  ... 
doi:10.3390/jlpea10030028 fatcat:hzc4ubk3cbh7tegmnptw7jyzei

Binary Addition in Resistance Switching Memory Array by Sensing Majority

John Reuben
2020 Micromachines  
The flow of data between processing and memory units in contemporary computing systems is their main performance and energy-efficiency bottleneck, often referred to as the 'von Neumann bottleneck' or '  ...  Emerging resistance switching memories (memristors) show promising signs to overcome the 'memory wall' by enabling computation in the memory array.  ...  Acknowledgments: The author would also like to thank Dietmar Fey, Chair of Computer Architecture, FAU for reviewing the manuscript.  ... 
doi:10.3390/mi11050496 pmid:32423171 fatcat:gfoa2ttabfentphzirf2dfwgh4

Microscopic quantum dynamics study on the noise threshold of fault-tolerant quantum error correction

Y. C. Cheng, R. J. Silbey
2005 Physical Review A. Atomic, Molecular, and Optical Physics  
These results provide insights into the fault-tolerant QEC process as well as useful information for designing the optimal fault-tolerant QEC circuit for particular physical implementation of quantum computer  ...  In addition, the effects of imprecision in projective measurements, collective bath, fault-tolerant repetition protocols, and level of parallelism in circuit constructions on the threshold values are also  ...  Fault-tolerant QEC circuits implementing either the three qubit bit-flip code or the five-qubit code were investigated, and the noise threshold for quantum memory and logical X gate were calculated by  ... 
doi:10.1103/physreva.72.012320 fatcat:spqlaror5ncghcmoeqrq6rcvzi

GPS-Based Vehicle Tracking System-on-Chip [article]

Adnan I. Yaqzan Prince Sultan University)
2019 arXiv   pre-print
In this paper, we build on a recently produced VTS (The Aram Locator) offering a system-on-chip (SOC) replacement of the current microcontroller-based implementation.  ...  Modern powerful reconfigurable systems are suited in the implementation of various data-stream, data-parallel, and other applications.  ...  Future work includes refining the proposed designs in order to eliminate the sequential alternation of the two main internal processes, and investigating larger buffering by providing more memory elements  ... 
arXiv:1904.09838v1 fatcat:xd2jor6afjhzbmqojbicxbjv2q

Supporting x86-64 address translation for 100s of GPU lanes

Jason Power, Mark D. Hill, David A. Wood
2014 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA)  
the translation rate by 6.8x on average), (2) TLB misses occur in bursts (60 concurrently on average), and (3) postcoalescer TLBs have high miss rates (29% average).  ...  Efficient memory sharing between CPU and GPU threads can greatly expand the effective set of GPGPU workloads.  ...  The authors would like to acknowledge Brad Beckmann, Karu Sankaralingam, members of the Multifacet research group, and our anonymous reviewers for their comments on the paper.  ... 
doi:10.1109/hpca.2014.6835965 dblp:conf/hpca/PowerHW14 fatcat:sonrdgcadbcwtopl2a4hfh72em

Wildly Heterogeneous Post-CMOS Technologies Meet Software (Dagstuhl Seminar 17061)

Jerónimo Castrillón-Mazo, Tei-Wei Kuo, Heike E. Riel, Matthias Lieber, Marc Herbstritt
2017 Dagstuhl Reports  
The end of exponential scaling in conventional CMOS technologies has been forecasted for many years by now.  ...  computing beyond current CMOS technology and to create long-term visions about a future hardware/software stack.  ...  Going 3D 3D integration enables the integration of heterogeneous technologies for logic, memory, communication, and sensing on a single chip.  ... 
doi:10.4230/dagrep.7.2.1 dblp:journals/dagstuhl-reports/MazoKRL17 fatcat:ive75xhpbvgwfb5hdavdixhkpu

Throughput-optimized implementations of QUAD

Jason R. Hamlet, Robert W. Brocato
2015 Journal of Cryptographic Engineering  
The purpose of our work was to first find the baseline performance of QUAD implementations, then to optimize our implementations for throughput.  ...  The software implementations target both a personal computer and an ARM microprocessor. The hardware implementations target field programmable gate arrays.  ...  We investigated design variations to improve the speed of the implementations, and we discussed methods for further improving the software and hardware approaches in future work.  ... 
doi:10.1007/s13389-015-0109-y fatcat:hr46y53qpbedjge2zxm456j6ga

The energy efficiency of IRAM architectures

Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce McGaughy, David Patterson, Tom Anderson, Katherine Yelick
1997 Proceedings of the 24th annual international symposium on Computer architecture - ISCA '97  
on-chip than a traditional SRAM cache design in a logic process.  ...  IRAM architectures, which combine DRAM and a processor on the same chip in a DRAMprocess, are more energy e$cient than conventional systems, The high density of DRAMpermits a much larger amount of memory  ...  Acknowledgments We are grateful to Dan Dobberpuhl, Dan Murray, nnd Sribnlnn Santhanam of Digital Equipment Corporation for their helpful nn-  ... 
doi:10.1145/264107.264214 dblp:conf/isca/FrommPCKMPAY97 fatcat:kqqk5q5dnbbxvd67bynqxgf3im

The energy efficiency of IRAM architectures

Richard Fromm, Stylianos Perissakis, Neal Cardwell, Christoforos Kozyrakis, Bruce McGaughy, David Patterson, Tom Anderson, Katherine Yelick
1997 SIGARCH Computer Architecture News  
on-chip than a traditional SRAM cache design in a logic process.  ...  IRAM architectures, which combine DRAM and a processor on the same chip in a DRAMprocess, are more energy e$cient than conventional systems, The high density of DRAMpermits a much larger amount of memory  ...  Acknowledgments We are grateful to Dan Dobberpuhl, Dan Murray, nnd Sribnlnn Santhanam of Digital Equipment Corporation for their helpful nn-  ... 
doi:10.1145/384286.264214 fatcat:olda2bmfofhbpcidklv35mkhea

Parallelisation Techniques for the Dual Reciprocity and Time-Dependent Boundary Element Method Algorithms

Tim Bashford, Kelvin Donne, Arnaud Marotin, Ala Al-Hussany
2017 International Journal of Computational Methods & Experimental Measurements  
In order to achieve sensible solution times for realistic 3D problems with large meshes, a range of optimisation techniques are considered, and a number of parallelisation techniques applied: shared memory  ...  The Dual Reciprocity BEM (DRBEM) and the Time-Dependent BEM (TDBEM) are considered in the context of radiative and time-dependent thermal transport, respectively.  ...  An investigation into the improvement in speed which can be achieved through modifying the internal pole count, and the resultant impact on accuracy, is the subject of future work.  ... 
doi:10.2495/cmem-v5-n3-395-403 fatcat:kcdzkqlpjbbirj3lrjp3m5atcu

Simultac Fonton: A Fine-Grain Architecture for Extreme Performance beyond Moore's Law

2017 Supercomputing Frontiers and Innovations  
The bottlenecks imposed by this heritage are the emphasis on ALU/FPU utilization, single instruction issue and sequential consistency, and the separation of memory and processing logic ("von Neumann bottleneck  ...  Here the authors explore the possibility and implications of one class of non von Neumann architecture based on cellular structures, asynchronous multi-tasking, distributed shared memory, and message-driven  ...  Simultac Fonton The Simultac architecture currently investigated by the authors is but one of possible species of CCA.  ... 
doi:10.14529/jsfi170203 fatcat:2us4eiaoyvgdrnldlljjlrntae

A TDMA Ethernet Switch for Dynamic Real-Time Communication

Gonzalo Carvajal, Sebastian Fischmeister
2010 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines  
The switch, called the Network Code Switch bases on the NetFPGA system and executes flexible but verifiable state-based schedules encoded in the Network Code programming language.  ...  In this work, we introduce a switch that implements a programmable dedicated time-triggered packet switching mechanism on top of Ethernet.  ...  Acknowledgment The authors would like to thank Robert Trausmuth and Kevin Perry for their assistant in the Network Code Processor, Ronald Valenzuela for his work on the PCI and Linux interfaces, and Israel  ... 
doi:10.1109/fccm.2010.27 dblp:conf/fccm/CarvajalF10 fatcat:p6qaclwftzhbzgmzppbh5tqhzq

Balancing Error and Dissipation in Computing [article]

P. M. Riechers, A. B. Boyd, G. W. Wimsatt, J. P. Crutchfield
2020 arXiv   pre-print
The reciprocity (self-invertibility) of a computation is a stricter condition for thermodynamic efficiency than logical reversibility (invertibility), the latter being the root of Landauer's work bound  ...  Beyond engineered computation, the results identify a generic error-dissipation tradeoff in steady-state transformations of genetic information carried out by biological organisms.  ...  The typical implementation requires two bistable memory elements (M In particular, since networks of NAND gates are sufficient for universal computation, the NAND gate is worthy of immediate investigation  ... 
arXiv:1909.06650v2 fatcat:wahvgbafyvehpjjn2tksw2nttu

Machine Intelligence Techniques in VLSI Hardware

2019 International Journal of Engineering and Advanced Technology  
The application of programming methods in VLSI hardware can be both difficult and reasonable.  ...  Deep architectures, stratified temporal reminiscences and memory networks square measure a number of up-to-date approaches in this analysis area.  ...  The discovery that cerebral mantle structures by protocols and software integration have always been the basis for the greater part of state-of-the-art computer engineering programs and theory [1] .  ... 
doi:10.35940/ijeat.f1302.0986s319 fatcat:4zavqzwunfaxnjg37r7wdk6u6u

Building Run-Time Reconfigurable Systems from Tiles [chapter]

Gareth Lee, George Milne
2003 Lecture Notes in Computer Science  
This paper describes a component-based methodology tailored to the design of reconfigurable systems of field programmable logic.  ...  We present a statebased model for managing a hierarchical structure of tiles in a reconfigurable system and show how our approach allows automatic garbage collection techniques to be applied for reclaiming  ...  In future work we intend to investigate asynchronous dispatch of messages since this would allow the controlling objects to be executed on multiple supervisory processors.  ... 
doi:10.1007/978-3-540-45234-8_25 fatcat:3g26k7eizbbexb24a2ez5zrwlq
« Previous Showing results 1 — 15 out of 47,872 results