Filters








36 Hits in 8.7 sec

SET and noise fault tolerant circuit design techniques: Application to 7nm FinFET

A. Calomarde, E. Amat, F. Moll, J. Vigara, A. Rubio
2014 Microelectronics and reliability  
In this paper, we present a novel design style that reduces the impact of radiation-induced single event transients (SET) on logic circuits, and enhances the robustness in noisy environments.  ...  a Single Event Transient.  ...  This research work has been undertaken with the support of the Spanish MINECO (JCI-2010-07083 and TEC2008-01856 with FEDER funds).  ... 
doi:10.1016/j.microrel.2013.12.018 fatcat:vque7zamjvacbikketthw46piu

Comparative soft error evaluation of layout cells in FinFET technology

L. Artola, G. Hubert, M. Alioto
2014 Microelectronics and reliability  
This work presents a comparative soft error evaluation of logic gates in bulk FinFET technology from 65-down to 32-nm technology generations.  ...  Single Event Transients induced by radiations are modeled with the MUSCA SEP3 tool, which explicitly accounts for the layout and the electrical properties of transistors.  ...  This work presents a comparative Single Event Transient (SET) evaluation of logic gates for different layout styles in FinFET technology for different technologies.  ... 
doi:10.1016/j.microrel.2014.07.109 fatcat:e2nrf7kj2zaf5h5oo6djefvoea

Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology

Y.Q. de Aguiar, L. Artola, G. Hubert, C. Meinhardt, F.L. Kastensmidt, R.A.L. Reis
2017 Microelectronics and reliability  
This paper presents a comparative analysis of different Majority Voter designs in 7nm FinFET under radiation effects. The MUSCA SEP3 tool is used to estimate the SER of each circuit.  ...  Radiation-induced soft error is an ever-increasing concern in the microelectronic industry in order to provide reliable VLSI systems at advanced technology nodes.  ...  Acknowledgments This work is sponsored by the Brazilian National Council for the Improvement of Higher Education -CAPES.  ... 
doi:10.1016/j.microrel.2017.06.077 fatcat:jkm5zog2qffs7liany7fidrglq

SE Response of Guard-Gate FF in 16-nm and 7-nm Bulk FinFET Technologies

Jingchen Cao, Lyuan Xu, Bharat L. Bhuva, Rita Fung, Shi-Jie Wen, Carlo Cazzaniga, C. Frost
2020 IEEE Transactions on Nuclear Science  
Electrical Engineering SE Response of Guard-Gate FF in 16-nm and 7-nm Bulk FinFET Technologies Jingchen Cao Dissertation under the direction of Professor Bharat Bhuva With scaling of CMOS technology, single  ...  In this work, a Guard-Gate Flip-Flop (GG-FF) design with improved single event reliability (SER) has been investigated.  ...  Such designs reduce single-event error rates (SER) to extremely low levels [5- 9].  ... 
doi:10.1109/tns.2020.2983140 fatcat:fuov67qdifcbrfde3acoq4ybrq

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects

Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Leticia Bolzani Poehls, Tiago Balen
2020 2020 IEEE Latin-American Test Symposium (LATS)  
In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects.  ...  to increase sensitivity to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities as Static Random-Access Memories (SRAMs).  ...  Results of TCAD single event transient simulations The heavy-ion simulation considers the particle strike in the corresponding time of 10 ps.  ... 
doi:10.1109/lats49555.2020.9093667 dblp:conf/latw/CopettiMTHPB20 fatcat:v5txx2j5bfgrngnw2q76l74u7a

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects

Thiago Copetti, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Letícia Bolzani Poehls, Tiago Balen
2021 Journal of electronic testing  
In this context, this paper proposes to investigate the impact of ionizing particles on the reliability of FinFET-based SRAMs in the presence of weak resistive defects.  ...  to Single Event Upsets (SEUs) caused by ionizing particles, especially in blocks with higher transistor densities such as Static Random-Access Memories (SRAMs).  ...  Comparing the data, it is verified that Simulating Single Event Transient using TCAD The heavy-ion simulation considers the particle strike in the corresponding time of 10 ps and the ion track according  ... 
doi:10.1007/s10836-021-05949-x fatcat:vkyw3ho4jbdkbc5wppxjw7n54a

Soft Error Impact on FinFET and CMOS XOR Logic Gates

Rafael N. M. Oliveira, Cristina Meinhardt
2020 Journal of Integrated Circuits and Systems  
Thechallenges change significantly as feature size are smaller, evenfor FinFET devices. The effects of Single Event Transientare dependent of the circuit topology.  ...  Finally, the com-plete set of information provided in this work support design-ers to choose the most appropriate XOR topology accordingthe specific design requirements.  ...  ACKNOWLEDGEMENTS This work was financed in part by National Council for Scientific and Technological Development CNPq and the Propesq/UFSC.  ... 
doi:10.29292/jics.v15i2.131 fatcat:nxkjgwzxf5ht7e7sweyi6256vy

2020 Index IEEE Transactions on Nuclear Science Vol. 67

2020 IEEE Transactions on Nuclear Science  
., +, TNS June 2020 1045-1048 Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10.  ...  ., +, TNS June 2020 939-945 Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Contain- ing Boron-10.  ...  Gamma-rays Simulation of High-Altitude Nuclear Electromagnetic Pulse Using a Modified Model of Scattered Gamma. 2474 -2480 Band Gap Variation and Trap Distribution in Transparent Garnet Scintillator  ... 
doi:10.1109/tns.2020.3048765 fatcat:zgygdayuenh5nftvetqv3mfxle

Geometry Dependence of Total-Dose Effects in Bulk FinFETs

I. Chatterjee, E. X. Zhang, B. L. Bhuva, R. A. Reed, M. L. Alles, N. N. Mahatme, D. R. Ball, R. D. Schrimpf, D. M. Fleetwood, D. Linten, E. Simoen, J. Mitard (+1 others)
2014 IEEE Transactions on Nuclear Science  
Single Event Effects in MOS Devices Single Event Effects (SEE) in microelectronics are caused when highly energetic particles present in the natural space environment (e.g., protons, neutrons, alpha particles  ...  Depending on several factors, the particle strike may cause no observable effect, a transient disruption of circuit operation, a change of logic state, or even permanent damage to the device or integrated  ... 
doi:10.1109/tns.2014.2367157 fatcat:tbwaubvtzfhn7j3bhqkqp42jj4

A Survey of fault models and fault tolerance methods for 2D bus-based multi-core systems and TSV based 3D NOC many-core systems [article]

Shashikiran Venkatesha, Ranjani Parthasarathi
2022 arXiv   pre-print
The article presents a gamut of fault tolerance solutions from logic level to processor core level in a multi-core and many-core scenario.  ...  A Surge of interest is noticeable in recent times in formulating fault and failure models, understanding failure mechanism and strategizing fault mitigation methods for improving the reliability of the  ...  (a) Single Event Transient (SET): -A small glitch in the logic circuit or changes in the state of the flip-flop or memory elements are the symptoms of SET occurrence [39] .  ... 
arXiv:2203.07830v1 fatcat:dsbx3o4v3femhi5d6kfrurzuoi

Superimposed In-Circuit Fault Mitigation for Dynamically Reconfigurable FPGAs

Alexandra Kourfali, David Merodio Codinachs, Dirk Stroobandt
2017 2017 17th European Conference on Radiation and Its Effects on Components and Systems (RADECS)  
Predictive simulation applications to radiation hardened analog circuits design are discussed.  ...  Tomsk Polytechnic University, 6 National Research Nuclear University "MEPhI", 7 Novosibirsk State University Radiation hardened bandgap voltage reference was designed using Verilog-A physical modeling of  ...  Radiation Robustness of FinFET XOR Circuits PE-5 Effective Characterization of Radiation-induced SET on Flash-based FPGAs Luca Sterpone 1 , Sarah Azimi 1 1 Politecnico di Torino Single Event Transients  ... 
doi:10.1109/radecs.2017.8696242 fatcat:frcrfuza2fdstitbsjoda5sn4y

Practical Strategies for Power-Efficient Computing Technologies

L. Chang, D.J. Frank, R.K. Montoye, S.J. Koester, B.L. Ji, P.W. Coteus, R.H. Dennard, W. Haensch
2010 Proceedings of the IEEE  
Solutions for the critical elements of a practical computing system are discussed, including the underlying logic device, associated cache memory, off-chip interconnect, and power delivery system.  ...  By simultaneously considering all three perspectives, the major issues involved in improving power efficiency in light of performance and area constraints are identified.  ...  Acknowledgment The authors would like to thank all of their colleagues at IBM for invaluable discussions, criticism, and guidance. In particular, the authors would like to acknowledge A.  ... 
doi:10.1109/jproc.2009.2035451 fatcat:hp3zqxde7vakvd7xzvu7l6wcga

Radiation Tolerant Electronics

Paul Leroux
2019 Electronics  
Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits  ...  The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.  ...  The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.  ... 
doi:10.3390/electronics8070730 fatcat:wjo5prr5xjeqtlhxlj4kqz5st4

Radiation Effects in Advanced and Emerging Nonvolatile Memories

Matthew J. Marinella
2021 IEEE Transactions on Nuclear Science  
Radiation effects relevant to each of these memories are described, including the physics of and errors caused by total ionizing dose, displacement damage, and single-event effects, with an eye toward  ...  the future role of emerging technologies in radiation environments.  ...  Single-event upsets occur readily in the floating cell at LETs of less than 10 MeV·cm 2 /mg.  ... 
doi:10.1109/tns.2021.3074139 fatcat:sosgjpsninerbkkaocswmutakm

Confronting the Variability Issues Affecting the Performance of Next-Generation SRAM Design to Optimize and Predict the Speed and Yield

Jeren Samandari-Rad, Matthew Guthaus, Richard Hughey
2014 IEEE Access  
We present the access-time variation calculated by our model for the future 16-nm node and compare it to 45-nm and 180-nm (Sections VIB-VIE, VIH) to show the larger impact of process variations in increasingly  ...  In this paper, we develop methods for robust and resilient six-transistor-cell static random access memory (6T-SRAM) designs that mitigate the effects of device and circuit parameter variations.  ...  Table 2 [50] shows the single event upset (SEU) rate per microprocessor in various technologies [51] .  ... 
doi:10.1109/access.2014.2323233 fatcat:hsqprvcb2zhalegj2gtletna7e
« Previous Showing results 1 — 15 out of 36 results