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Generic Low-Latency NoC Router Architecture for FPGA Computing Systems

Ye Lu, John McCanny, Sakir Sezer
2011 2011 21st International Conference on Field Programmable Logic and Applications  
This has been designed to be scalable at system level to fully exploit the characteristics and constraints of FPGA based systems, rather than custom ASIC technology.  ...  The architecture proposed can be easily migrated across many FPGA families to provide flexible, robust and cost-effective NoC solutions suitable for the implementation of high-performance FPGA computing  ...  To date, both packet-switched and time-multiplexed NoC designs for FPGA have been investigated [4] .  ... 
doi:10.1109/fpl.2011.25 dblp:conf/fpl/LuMS11 fatcat:itdlmvmyibenrjtmhxk3dyc6ei

Analysis of FPGA/FPIC switch modules

Yao-Wen Chang, Kai Zhu, Guang-Ming Wu, D. F. Wong, C. K. Wong
2003 ACM Transactions on Design Automation of Electronic Systems  
Switch modules are the most important component of the routing resources in FPGAs/FPICs.  ...  We present a network-flow-based approximation algorithm for this problem.  ...  ACKNOWLEDGMENTS The authors would like to thank Dr. Glenn Lai for many helpful suggestions, Shashidhar Thakur for providing the ILP analyzer, and anonymous reviewers for very constructive comments.  ... 
doi:10.1145/606603.606605 fatcat:2dr5bm3wj5cdtgc77pnpuy6chq

In-network online data analytics with FPGAs

Ryan Cooke, Suhaib A. Fahmy
2017 2017 27th International Conference on Field Programmable Logic and Applications (FPL)  
The low overhead of deploying FPGAs in such a scenario is key to the feasibility of this idea, and hence the management framework must be capable enough to abstract low level operations.  ...  Results can be used to validate the model detailed in Section III, and be used with the model to investigate what happens when the network is scaled up.  ... 
doi:10.23919/fpl.2017.8056761 dblp:conf/fpl/CookeF17 fatcat:ot62zfhcgbgoxccwwbdj5qtkra

Reconfigurable Computing Cluster (RCC) Project: Investigating the Feasibility of FPGA-Based Petascale Computing

Ron Sass, William V. Kritikos, Andrew G. Schmidt, Srinivas Beeravolu, Parag Beeraka
2007 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)  
The Reconfigurable Computing Cluster (RCC) project is a multi-institution, multi-disciplinary project investigating the use of FPGAs to build cost-effective petascale computers.  ...  These results characterize key subsystems -including the system software, network performance, memory bandwidth, power consumption of nodes in the cluster. Results suggest that the approach is sound.  ...  FPGA-based compute nodes, a novel data network, and two 48-port Ethernet network switches comprise the core components of the cluster.  ... 
doi:10.1109/fccm.2007.62 dblp:conf/fccm/SassKSBB07 fatcat:umj4bfkikzhinj6cnydv232q3m

Software-defined networking control plane for seamless integration of multiple silicon photonic switches in Datacom networks

Yiwen Shen, Maarten H. N. Hattink, Payman Samadi, Qixiang Cheng, Ziyiz Hu, Alexander Gazman, Keren Bergman
2018 Optics Express  
The integration of a silicon photonics-based optical switching fabric within electronic Datacom architectures requires novel network topologies and arbitration strategies to effectively manage the active  ...  Silicon photonics based switches offer an effective option for the delivery of dynamic bandwidth for future large-scale Datacom systems while maintaining scalable energy efficiency.  ...  In this work, we investigate the feasibility and performance of integrating silicon photonic circuit switching in conventional electronic Datacom network architectures, extending from [15] .  ... 
doi:10.1364/oe.26.010914 pmid:29716021 fatcat:qvbied6ghffp5fmtx4smonmyu4

Efficient multi-standard cognitive radios on FPGAs

Thinh H. Pham, Suhaib A. Fahmy, Ian Vince McLoughlin
2014 2014 24th International Conference on Field Programmable Logic and Applications (FPL)  
FPGA knowledge.  ...  This work explores the possible techniques for designing multi-standard radios on FPGAs, and explores how partial reconfiguration can be leveraged in a way that is amenable for domain experts with minimal  ...  As a result, when switching from one standard to another, only part of the FPGA needs to be reconfigured.  ... 
doi:10.1109/fpl.2014.6927380 dblp:conf/fpl/PhamFM14 fatcat:w6cnmyzaebhznozmu2abgpq3le

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA [chapter]

Vinod Pangracious, Zied Marrakchi, Emna Amouri, Habib Mehrez
2013 Lecture Notes in Computer Science  
Compared to 3D Mesh-based FPGA, the 3D Tree-based FPGA design reduces the number of TSVs by 29% and a performance improvement of 53% recorded in our place and route experiments.  ...  development of a Tree-based multilevel interconnect network is a major challenge for Tree-based FPGA.  ...  An accurate ST 130nm transistor level technology models were used to investigate switch, figure 5 , where the upward, downward and feedback interconnection networks are marked.  ... 
doi:10.1007/978-3-642-36812-7_19 fatcat:ahlaya2qhzh33jrueiuctinqoq

Virtualization of Programmable Forwarding Planes with P4VBox

Pablo Rodrigues, Mateus Saquetti, Guilherme Bueno, Weverton Cordeiro, Jose Azambuja
2021 Journal of Integrated Circuits and Systems  
Recent investigations began assessing the feasibility of virtualization in Programmable Data Planes (PDP).  ...  P4VBox provides the execution of multiple P4 based switch instances running in parallel, with the ability of hot-swapping through full and partial reconfiguration.  ...  ACKNOWLEDGEMENTS The authors thank CNPq and FAPERGS for the financial support to this work.  ... 
doi:10.29292/jics.v16i2.329 fatcat:us6klarmijhntbqraped7sawzi

On the Interaction Between Power-Aware Computer-Aided Design Algorithms for Field-Programmable Gate Arrays

Julien Lamoureux, Steven J. E. Wilton
2005 Journal of Low Power Electronics  
The majority of the overall energy reduction was achieved during the technology mapping and clustering stages of the power-aware FPGA CAD flow.  ...  Estimating energy using very detailed post-route power and delay models, we determine the gains obtained by our power-aware technology mapping, clustering, placement, and routing algorithms and investigate  ...  The edges of the Boolean networks are annotated with switching activity values.  ... 
doi:10.1166/jolpe.2005.023 fatcat:pwz2zdnjrnggvm7r6aifcvka2u

On optimal hyperuniversal and rearrangeable switch box designs

Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung
2003 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
FPGAs), switch box designs, and communication switching network designs.  ...  We apply the design scheme to rearrangeable switching network designs targeting for applications of connecting multiple terminals (e.g., teleconferencing).  ...  In a circuit-switching-based communication network, such as a traditional telephone network [1] , [2] , switch boxes are used to set up physical connections for communication parties.  ... 
doi:10.1109/tcad.2003.819430 fatcat:f6ehmu4vnfabxodl35cizwrtqi

Interconnect synthesis for reconfigurable multi-FPGA architectures [chapter]

Vinoo Srinivasan, Shankar Radhakrishnan, Ranga Vemuri, Jeff Walrath
1999 Lecture Notes in Computer Science  
The desired interconnections among the fpgas are speci ed as in the form of a netlist.  ...  Most recon gurable multi-fpga architectures have a programmable interconnection network that can be recon gured to implement di erent i n terconnection patterns between the fpgas and memory devices on  ...  adaptive recon gurable computing systems. sparcs provides automatic tools that perform temporal partitioning, spatial partitioning and high-level synthesis targeted toward dynamically recon gurable multi-fpga  ... 
doi:10.1007/bfb0097943 fatcat:e76cwanlfnaglphtrqwpkrrpf4

Hoplite: Building austere overlay NoCs for FPGAs

Nachiket Kapre, Jan Gray
2015 2015 25th International Conference on Field Programmable Logic and Applications (FPL)  
This design style simplifies the engineering of FPGA overlay networks in two fundamental ways: (1) The use of unidirectional torus instead of a bidirectional network enables simpler switching and control  ...  Specifically, we investigate the impact of bufferless routing on FPGA NoC implementation cost and on performance in terms of latency and bandwidth.  ... 
doi:10.1109/fpl.2015.7293956 dblp:conf/fpl/KapreG15 fatcat:3mb2mxqy7bdtlg4xknn3dvwlda

Quantifying the latency benefits of near-edge and in-network FPGA acceleration

Ryan A. Cooke, Suhaib A. Fahmy
2020 Proceedings of the Third ACM International Workshop on Edge Systems, Analytics and Networking  
This paper evaluates the the implications of these offloading approaches using a case study neural network based image classification application, quantifying both the computation and communication latency  ...  To address latency concerns, cloudlets, in-network computing, and more capable edge nodes are all being explored as a way of moving processing capability towards the edge of the network.  ...  ACKNOWLEDGMENTS This work was supported in part by The Alan Turing Institute under the UK EPSRC grant EP/N510129/1.  ... 
doi:10.1145/3378679.3394534 dblp:conf/eurosys/CookeF20 fatcat:pzl4sxoklzgylc4uprw67dzo5y

Algorithms for an FPGA switch module routing problem with application to global routing

S. Thakur, Yao-Wen Chang, D.F. Wong, S. Muthukrishnan
1997 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Using our solution to the switch module routing problem, we propose a new metric to estimate the congestion in each switch module in the FPGA.  ...  They used it to evaluate the routability properties of switch modules which they proposed. Only an approximation algorithm for the problem was proposed by them.  ...  ACKNOWLEDGMENT The authors thank Prof. S. Brown of the University of Toronto for providing them with the CGE and SEGA packages. Also, the authors thank K.  ... 
doi:10.1109/43.559330 fatcat:lq6dejxepfaq7gsiqx6fm4cqki

ReDCN: A Dynamic Bandwidth Enabled Optical Reconfigurable Data Center Network [chapter]

Xinwei Zhang, Zuoqing Zhao, Yisong Zhao, Yuanzhi Guo, Xuwei Xue, Bingli Guo, Shanguo Huang
2021 Frontiers in Artificial Intelligence and Applications  
Numerical investigations validate that the network performance of packet loss after reconfiguration decreases by 58.5%, and the end-to-end latency decreases by 63.8% with comparison to the network with  ...  A reconfigurable optical data center network is proposed, in which the optical bandwidth can be automatically reconfigured by reallocating time slots based on the real time traffic.  ...  Acknowledgements The project was supported by Fund of State Key Laboratory of Information Photonics and Optical Communications (Beijing University of Posts and Telecommunications) (No.  ... 
doi:10.3233/faia210451 fatcat:yxxtbpcat5es5l5figy2y4wjoy
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