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Introduction to partial time composability for COTS multicores

Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Luca Fossati, Marco Zulianello, Francisco J. Cazorla
2015 Proceedings of the 30th Annual ACM Symposium on Applied Computing - SAC '15  
Finally, we show how various degrees of time composability can help breaking this knot.  ...  In singlecore processors timing analysis involves a step of Execution Time Analysis at task level that yields an Execution Time Bound (ETB) for the task, and one of schedulability analysis, where the scheduling  ...  Jaume Abella has been partially supported by the MINECO Ramon y Cajal fellowship RYC-2013-14717.  ... 
doi:10.1145/2695664.2695954 dblp:conf/sac/FernandezAQVFZC15 fatcat:l2otp33dc5cuph7zdqiifeupy4

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors

Gabriel Fernandez, Jaume Abella, Eduardo Quinones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla
2015 2015 IEEE 18th International Symposium on Real-Time Distributed Computing  
The much-sought property of time composability [28], [15] , when transposed to a multicore processor, stipulates that the timing behavior of an individual task is not affected by the activity of its co-runners  ...  To help loosen this knot we present an approach that acknowledges different flavors of time composability, examining in detail the variant intended for partitioned scheduling, which we evaluate on two  ...  Agency under Contract 789.2013; and COST Action IC1202, Timing Analysis On Code-Level (TACLe).  ... 
doi:10.1109/isorc.2015.43 dblp:conf/isorc/FernandezAQFZVC15 fatcat:zbxdavl4nnarze5frhrkyckf7e

Seeking Time-Composable Partitions Of Tasks For Cots Multicore Processors

Gabriel Fernandez, Jaume Abella, Eduardo Qui˜nones, Luca Fossati, Marco Zulianello, Tullio Vardanega, Francisco J. Cazorla
2015 Zenodo  
The timing verification of real-time single core systems involves a timing analysis step that yields an Execution Time Bound (ETB) for each task, followed by a schedulability analysis step, where the scheduling  ...  The advent of multicore processors challenges the viability of this two-step approach because several complex contention effects at the processor level arise that cause tasks to be unable to make progress  ...  Agency under Contract 789.2013; and COST Action IC1202, Timing Analysis On Code-Level (TACLe).  ... 
doi:10.5281/zenodo.55525 fatcat:6xsqiwfjjjhvdjhxzskj7qkuby

On the tailoring of CAST-32A certification guidance to real COTS multicore architectures

Irune Agirre, Jaume Abella, Mikel Azkarate-Askasua, Francisco J. Cazorla
2017 2017 12th IEEE International Symposium on Industrial Embedded Systems (SIES)  
The use of Commercial Off-The-Shelf (COTS) multicores in real-time industry is on the rise due to multicores' potential performance increase and energy reduction.  ...  the difficulties of the application of CAST-32A to a real multicore processor, the NXP P4080.  ...  Jaume Abella has been partially supported by the MINECO under Ramon y Cajal grant RYC-2013-14717.  ... 
doi:10.1109/sies.2017.7993376 dblp:conf/sies/AgirreAAC17 fatcat:kzuqu6bqercmjleerp5sfrtwl4

Identifying the sources of unpredictability in COTS-based multicore systems

Dakshina Dasari, Benny Akesson, Vincent Nelis, Muhammad Ali Awan, Stefan M. Petters
2013 2013 8th IEEE International Symposium on Industrial Embedded Systems (SIES)  
COTS-based multicores are now the preferredchoice for hosting embedded applications owing to their immensecomputational capabilities, small form factor and low powerconsumption.  ...  However, the underlyingarchitecture of commercially available multicores is extremelycomplex and non-amenable to straight-forward timing analysis.In this paper, we highlight the architectural features  ...  INTRODUCTION Multicores developed using Commercially available Off-The-Shelf (COTS) components have become the preferred choice in the design of embedded systems.  ... 
doi:10.1109/sies.2013.6601469 dblp:conf/sies/DasariANAP13 fatcat:dg5rkpigebce7fkmpmbzry3fhm

Resource Usage Templates And Signatures For Cots Multicore Processors

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla
2015 Zenodo  
This dependence reduces time composability and constrains incremental verification.  ...  Upper bounding the execution time of tasks running on multicore processors is a hard challenge.  ...  Agency under Contract 789.2013 and NPI Contract 40001102880; and COST Action IC1202, Timing Analysis On Code-Level (TACLe).  ... 
doi:10.5281/zenodo.55517 fatcat:ledfi46spbcwvelh3ree2jif2i

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding [chapter]

Enrique Díaz, Mikel Fernández, Leonidas Kosmidis, Enrico Mezzetti, Carles Hernandez, Jaume Abella, Francisco J. Cazorla
2017 Lecture Notes in Computer Science  
In this paper we propose MC2, a technique for multilevel-cache multicores that combines deterministic and probabilistic jitter-bounding approaches to reliably handle both the variability in execution time  ...  We evaluate MC2 on a COTS quad-core LEON-based board and our initial results show how it effectively captures cache and multicore contention in pWCET estimates with respect to actual observed values.  ...  The partially Time Composable (pTC) model presented in this section trades time composability to tighten WCET estimates.  ... 
doi:10.1007/978-3-319-60588-3_7 fatcat:mcwld7v5pbhnrkyypvmq226pf4

Increasing confidence on measurement-based contention bounds for real-time round-robin buses

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla
2015 Proceedings of the 52nd Annual Design Automation Conference on - DAC '15  
This dependence reduces time composability and constrains incremental verification.  ...  Upper bounding the execution time of tasks running on multicore processors is a hard challenge.  ...  Agency under Contract 789.2013 and NPI Contract 40001102880; and COST Action IC1202, Timing Analysis On Code-Level (TACLe).  ... 
doi:10.1145/2744769.2744858 dblp:conf/dac/FernandezJAQVC15 fatcat:xtgic4brm5aa7jmsn7xe6c2wxy

Response Time Analysis of COTS-Based Multicores Considering the Contention on the Shared Memory Bus

Dakshina Dasari, Bjorn Andersson, Vincent Nelis, Stefan M. Petters, Arvind Easwaran, Jinkyu Lee
2011 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications  
Secondly, we apply this model to analyze the worstcase response time for a set of tasks.  ...  The current industry trend is towards using Commerciallyavailable Off-The-Shelf (COTS) based multicores for developing realtimeembedded systems, as opposed to the usage of custom-madehardware.  ...  INTRODUCTION Currently, multicore processors are generic building blocks in the design of embedded real-time computing systems.  ... 
doi:10.1109/trustcom.2011.146 dblp:conf/trustcom/DasariANPEL11 fatcat:6ddskbym3vbg7avsdduxoflotq

Modelling multicore contention on the AURIXTM TC27x

Enrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla
2018 Proceedings of the 55th Annual Design Automation Conference on - DAC '18  
We propose a contention model for automotive multicores that balances time-composability with tightness by exploiting available information on contenders.  ...  Worst-case execution time (WCET) estimates are required as early as possible in the software development, to enable prompt detection of timing misbehavior.  ...  INTRODUCTION Automotive industry is increasingly adopting multicores as the reference computing solution for ECUs [1] [2] [3] .  ... 
doi:10.1145/3195970.3196077 dblp:conf/dac/DiazMKAC18 fatcat:xivbvnmrwnb3hcl6ywfmv3iiue

Multicore enablement for Cyber Physical Systems

Andreas Herkersdorf
2012 2012 International Conference on Embedded Computer Systems (SAMOS)  
The enablement of multicore technology for embedded and cyber-physical markets imposes serious challenges to industry and academia which can easily overwhelm the capabilities and capacities of individual  ...  This report documents the program and the outcomes of Dagstuhl Seminar 13052 "Multicore Enablement for Embedded and Cyber Physical Systems".  ...  Tighter integration leads to the need of more powerful central compute platforms wish to use COTS chips for reasons like possible lower cost (COTS are likely multicore devices or SoC) Matthias Pruksch  ... 
doi:10.1109/samos.2012.6404198 dblp:conf/samos/Herkersdorf12 fatcat:73whij7ozbfgpimxz4md3f4jii

Increasing Confidence On Measurement-Based Contention Bounds For Real-Time Round-Robin Buses

Gabriel Fernandez, Javier Jalle, Jaume Abella, Eduardo Quiñones, Tullio Vardanega, Francisco J. Cazorla
2015 Zenodo  
Deriving ubd for a bus can be done accurately when enough timing information is available, which is not often the case for commercial-of-the-shelf (COTS) processors.  ...  Contention among tasks concurrently running in a multicore has been deeply studied in the literature specially for on-chip buses.  ...  Agency under Contract 789.2013 and NPI Contract 40001102880; and COST Action IC1202, Timing Analysis On Code-Level (TACLe).  ... 
doi:10.5281/zenodo.55515 fatcat:26mmwp5tgva5hosmil6ncde5tu

PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis

Francisco J. Cazorla, Jaume Abella, Jan Andersson, Tullio Vardanega, Francis Vatrinet, Iain Bate, Ian Broster, Mikel Azkarate-Askasua, Franck Wartel, Liliana Cucu, Fabrice Cros, Glenn Farrall (+15 others)
2016 2016 Euromicro Conference on Digital System Design (DSD)  
In this paper we relate the current state of practice in measurement-based timing analysis, the predominant choice for industrial developers, to the proceedings of the PROXIMA 1 project in that very field  ...  The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing  ...  ACKNOWLEDGEMENTS The research leading to these results has received funding from the European Community's Seventh  ... 
doi:10.1109/dsd.2016.22 dblp:conf/dsd/CazorlaAAVVBBAW16 fatcat:qidopagxeffazixbhtmmfaypxa

Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art

Gabriel Fernandez, Jaume Abella, Eduardo Quiñones, Christine Rochange, Tullio Vardanega, Francisco J. Cazorla, Marc Herbstritt
2014 Worst-Case Execution Time Analysis  
The real-time systems community has over the years devoted considerable attention to the impact on execution timing that arises from contention on access to hardware shared resources.  ...  This sparseness makes it difficult for any reader to form a coherent picture of the problem and solution space.  ...  The research leading to this work has received funding from: COST Action IC1202, Timing Analysis On Code-Level (TACLe); and the parMERASA and PROX-IMA grant agreements (respectively no. 287519 and 611085  ... 
doi:10.4230/oasics.wcet.2014.31 dblp:conf/wcet/FernandezAQRVC14 fatcat:xfhpnrtmf5a65ek3upravfesca

On the convergence of mainstream and mission-critical markets

Sylvain Girbal, Miquel Moretó, Arnaud Grasset, Jaume Abella, Eduardo Quiñones, Francisco J. Cazorla, Sami Yehia
2013 Proceedings of the 50th Annual Design Automation Conference on - DAC '13  
margins to guarantee either correctness or timing.  ...  Such convergence is fuelled by the common needs of both markets for more reliability, support for mission-critical functionalities and the challenge of harnessing the unsustainable increases in safety  ...  A.5 Modeling Alternatives In order to provide timing guarantees for future missioncritical systems running on multicore COTS, new timing analysis mechanisms have to be developed.  ... 
doi:10.1145/2463209.2488962 dblp:conf/dac/GirbalMGAQCY13 fatcat:zaswvzavorfwjg7fpkm4xblrsq
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