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Interconnection fabric design for tracing signals in post-silicon validation

Xiao Liu, Qiang Xu
2009 Proceedings of the 46th Annual Design Automation Conference on ZZZ - DAC '09  
Post-silicon validation has become an essential step in the design flow of today's complex integrated circuits.  ...  In this paper, we propose a novel trace signal interconnection fabric design to tackle the above problem. Experimental results on benchmark circuits show the efficacy of the proposed solution.  ...  ACKNOWLEDGEMENTS This work was supported in part by the General Research Fund CUHK417406, CUHK417807, and CUHK418708 from Hong Kong SAR Research Grants Council, and in part by a grant N_CUHK417/08 from  ... 
doi:10.1145/1629911.1630006 dblp:conf/dac/LiuX09 fatcat:quzfhmwwqrhbvmj7xuykgoib34

On signal tracing in post-silicon validation

Qiang Xu, Xiao Liu
2010 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC)  
It is increasingly difficult to guarantee the first silicon success for complex integrated circuit (IC) designs. Post-silicon validation has thus become an essential step in the IC design flow.  ...  Trace-based debug solution, however, involves non-trivial design for debug overhead. How to conduct signal tracing effectively for bug elimination is therefore a challenging task for IC designers.  ...  In Section III and Section IV, we discuss automated trace signal selection methodologies and interconnection fabric design for trace data transfer, respectively.  ... 
doi:10.1109/aspdac.2010.5419883 dblp:conf/aspdac/XuL10 fatcat:5ftlnjsgmbf6ro5vvlufbfvnhq

On efficient silicon debug with flexible trace interconnection fabric

Xiao Liu, Qiang Xu
2012 2012 IEEE International Test Conference  
In this paper, we propose a flexible trace interconnection fabric design that is able to overcome the above limitations, at the cost of little extra design-for-debug hardware.  ...  Therefore, a trace interconnection fabric is utilized to output either a subset of signals with multiplexor (MUX) network or compressed signatures with XOR network to the trace memory/port in each debug  ...  solely through pre-silicon verification, requiring post-silicon validation to catch bugs left in the design.  ... 
doi:10.1109/test.2012.6401539 dblp:conf/itc/LiuX12 fatcat:62a6kdkaifczjig35hluymbj34

A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems

Jianliang Gao, Jianxin Wang, Yinhe Han, Lei Zhang, Xiaowei Li
2012 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE)  
In addition, the on-chip interconnection fabric is extremely high hardware cost for the distributed trace signals.  ...  In the proposed scheme, a unified communication framework eliminates the requirement for interconnection fabric which is only used during debugging.  ...  Scan-based and trace-based technologies are common design-for-debug (DfD) to improve the visibility of internal signals for post-silicon debug [3] .  ... 
doi:10.1109/date.2012.6176427 dblp:conf/date/GaoWHZL12 fatcat:zfzhnathgbbttjcj6sxkbs3bay

On multiplexed signal tracing for post-silicon debug

Xiao Liu, Qiang Xu
2011 2011 Design, Automation & Test in Europe  
A novel trace signal grouping algorithm is presented to maximize the probability of catching the propagated evidences from design errors, considering the trace interconnection fabric design constraints  ...  Trace-based debug solutions facilitate to eliminate design errors escaped from pre-silicon verification and have gained wide acceptance in the industry.  ...  INTRODUCTION Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification [2, 6, 8] .  ... 
doi:10.1109/date.2011.5763116 dblp:conf/date/LiuX11 fatcat:kmdrmunpnraw3eeb3iohjd7key

A Post-Silicon Trace Analysis Approach for System-on-Chip Protocol Debug [article]

Yuting Cao, Hao Zheng, Sandip Ray, Jin Yang
2020 arXiv   pre-print
Reconstructing system-level behavior from silicon traces is a critical problem in post-silicon validation of System-on-Chip designs.  ...  This paper presents a trace analysis approach that exploits architectural models of the system-level protocols to reconstruct design behavior from partially observed silicon traces in the presence of ambiguous  ...  INTRODUCTION Post-silicon validation makes use of pre-production silicon integrated circuit (IC) to ensure that the fabricated system works as desired under actual operating conditions with real software  ... 
arXiv:2005.02550v1 fatcat:dzz72oc5rvhn5m6wnl4s6vlxwa

On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation

Xiao Liu, Qiang Xu
2010 2010 19th IEEE Asian Test Symposium  
Since tracing all speedpath-related signals can cause prohibited design for debug (DfD) overhead, we present an automated trace signal selection methodology that maximizes error detection probability under  ...  One of the most challenging problems in post-silicon validation is to identify those errors that cause prohibitive extra delay on speedpaths in the circuit under debug (CUD) and only expose themselves  ...  To the best of our knowledge, this is the first trace-based solution for debugging electrical errors in general logic circuits in post-silicon validation.  ... 
doi:10.1109/ats.2010.50 dblp:conf/ats/LiuX10 fatcat:lj4kere6kzd6zctoxerwodaxfq

Compact Models and Model Standard for 2.5D and 3D Integration

Qiaosha Zou, Yuan Xie
2014 Proceedings of SLIP (System Level Interconnect Prediction) on System Level Interconnect Prediction Workshop - SLIP '14  
This paper provides a summary of previous work on electrical modelings for 3D IC, with an emphasis on two key interconnect approaches: TSVs and RDLs.  ...  There are various approaches for 3D integration, including system-in-package (SiP), TSVbased 3D ICs, monolithic 3D ICs, and inductance/capacitance coupling 3D ICs, among which TSV-based 3D IC is the most  ...  A compact 3D/2.5D model standard for electrical behavior is urgently needed to aid electronic design automation tools for 3D design modeling and design validation.  ... 
doi:10.1145/2633948.2633955 dblp:conf/slip/Zou014 fatcat:jo4wzmsctzegjjr4nucxpqswbi

Intra-and Inter-Chip Transmission of Millimeter-Wave Interconnects in NoC-based Multi-Chip Systems

Rounak Singh Narde, Jayanti Venkataraman, Amlan Ganguly, Ivan Puchades
2019 IEEE Access  
The simulation results have been validated with fabricated antennas in different orientations on silicon dies that can communicate with inter-chip transmission coefficients ranging from −45 to −60 dB while  ...  Using measurements, a large-scale log-normal channel model is derived, which can be used for system-level architecture design.  ...  The width of the signal trace is 70µm. FIGURE 3 . 3 Silicon chips with antennas (ANT) in multi-chip system for simulation and fabrication.  ... 
doi:10.1109/access.2019.2931658 fatcat:jheqixi6kbdgzj6dw7oq4ba2la

Development of silicon interposer: towards an ultralow radioactivity background photodetector system [article]

Haibo Yang, Qidong Wang, Guofu Cao, Kali M. Melby, Khadouja Harouaka, Isaac J. Arnquist, Fengwei Dai, Liqiang Cao, Liangjian Wen
2022 arXiv   pre-print
In this work, based on double-sided TSV interconnect technology, we developed the first prototype of a silicon interposer with a size of 10 cm×10 cm and a thickness of 320 μm.  ...  However, interposers, used to provide mechanical support and signal routes between the photosensor and the electronics, are a bottleneck in building ultralow background photodetectors.  ...  Structure design TSV is the most critical process in silicon interposer fabrication [20] , which is also an important factor in the considerations of structure design.  ... 
arXiv:2207.09174v1 fatcat:dwoiu533hzc4hlf6uk7gjei55m

A reconfigurable design-for-debug infrastructure for SoCs

M. Abramovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, D. Miller
2006 Proceedings - Design Automation Conference  
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug.  ...  A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port.  ...  There is a huge difference between the variety and the sophistication of the tools available for pre-silicon verification and the lack of automation associated with post-silicon validation.  ... 
doi:10.1109/dac.2006.238683 fatcat:3fl4qqsutjd3te6jleaw5o6wgu

A reconfigurable design-for-debug infrastructure for SoCs

Miron Abramovici, Paul Bradley, Kumar Dwarakanath, Peter Levin, Gerard Memmi, Dave Miller
2006 Proceedings of the 43rd annual conference on Design automation - DAC '06  
In this paper we present a Design-for-Debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug.  ...  A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port.  ...  There is a huge difference between the variety and the sophistication of the tools available for pre-silicon verification and the lack of automation associated with post-silicon validation.  ... 
doi:10.1145/1146909.1146916 dblp:conf/dac/AbramoviciBDLMM06 fatcat:ojux2nb3wjfajnuu6bhp5pzfce

A silicon-based neural probe with densely-packed low-impedance titanium nitride microelectrodes for ultrahigh-resolution in vivo recordings

Richárd Fiáth, Bogdan Cristian Raducanu, Silke Musa, Alexandru Andrei, Carolina Mora Lopez, Chris van Hoof, Patrick Ruther, Arno Aarts, Domonkos Horváth, István Ulbert
2018 Biosensors & bioelectronics  
In this study, we developed and validated a single-shank silicon-based neural probe with 128 closely-packed microelectrodes suitable for high-resolution extracellular recordings.  ...  Moreover, the probe was developed with the specific goal to use it as a tool for the validation of electrophysiological data recorded with high-channel-count, high-density neural probes comprising integrated  ...  In vivo electrophysiological recordings The fabricated silicon probes were validated in the brain tissue of three animal species, namely, rats, mice and cats.  ... 
doi:10.1016/j.bios.2018.01.060 pmid:29414094 fatcat:kru3rptdz5dmveq7pob53idmny

A PDMS-Based Integrated Stretchable Microelectrode Array (isMEA) for Neural and Muscular Surface Interfacing

Liang Guo, G. S. Guvanasen, Xi Liu, C. Tuthill, T. R. Nichols, S. P. DeWeerth
2013 IEEE Transactions on Biomedical Circuits and Systems  
In this paper, this PDMS-based integrated stretchable MEA (isMEA) technology is demonstrated by an example design that packages a stretchable MEA with a small PCB.  ...  This paper describes an integrated technology for fabrication of PDMS-based stretchable microelectrode arrays (MEAs).  ...  These rigid-needle MEAs are typically fabricated using silicon, glass, and metals [2] - [8] .  ... 
doi:10.1109/tbcas.2012.2192932 pmid:23853274 fatcat:oqof2zlb7fcpxmmvmgmcpk2glm

A structured approach to post-silicon validation and debug using symbolic quick error detection

David Lin, Eshan Singh, Clark Barrett, Subhasish Mitra
2015 2015 IEEE International Test Conference (ITC)  
During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs).  ...  We present Symbolic Quick Error Detection (Symbolic QED), a structured approach to post-silicon validation and debug. Symbolic QED combines the following steps in a coordinated fashion: 1.  ...  Traditional post-silicon validation and debug techniques often rely on trace buffers to generate bug traces.  ... 
doi:10.1109/test.2015.7342397 dblp:conf/itc/LinSBM15 fatcat:nybzktfzxrbifalzt3tfv23q44
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