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Interconnect implications of growth-based structural models for VLSI circuits

Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu
2001 Proceedings of the 2001 international workshop on System-level interconnect prediction - SLIP '01  
Our work demonstrates the possibility of non-Rent based, yet equally plausible and well-fitting, structural models for VLSI circuits and their interconnections.  ...  This research investigates possible alternative power-law phenomena in VLSI circuits. In particular, we develop new random growth models and assess their implications for VLSI interconnect structure.  ...  Acknowledgments We thank Igor Markov and Stefanus Mantik for modifications to, and help with use of, the UCLA Capo placer.  ... 
doi:10.1145/368640.368730 dblp:conf/slip/ChengKL01 fatcat:skssgwmeofezbfmltfbgrhvj5m

On the relevance of wire load models

Kenneth D. Boese, Andrew B. Kahng, Stafanus Mantik
2001 Proceedings of the 2001 international workshop on System-level interconnect prediction - SLIP '01  
Our work demonstrates the possibility of non-Rent based, yet equally plausible and well-fitting, structural models for VLSI circuits and their interconnections.  ...  This research investigates possible alternative power-law phenomena in VLSI circuits. In particular, we develop new random growth models and assess their implications for VLSI interconnect structure.  ...  Acknowledgments We thank Igor Markov and Stefanus Mantik for modifications to, and help with use of, the UCLA Capo placer.  ... 
doi:10.1145/368640.368719 dblp:conf/slip/BoeseKM01 fatcat:tgmdlxz3pvafhiblfchm46zo5m

Circuit Modeling and Performance Analysis of Multi-Walled Carbon Nanotube Interconnects

Hong Li, Wen-Yan Yin, Kaustav Banerjee, Jun-Fa Mao
2008 IEEE Transactions on Electron Devices  
A compact equivalent circuit model of MWCNTs is presented for the first time, and the performance of MWCNT interconnects is evaluated and compared against traditional Cu interconnects, as well as Single-Walled  ...  This paper presents, for the first time, a detailed investigation of MWCNT-based interconnect performance.  ...  The significantly smaller signal delays of MWCNT interconnects at the global and intermediate levels have significant implications for nanoscale VLSI.  ... 
doi:10.1109/ted.2008.922855 fatcat:x65ual3gr5dkjnhkryvyeiw7ke

3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration

K. Banerjee, S.J. Souri, P. Kapur, K.C. Saraswat
2001 Proceedings of the IEEE  
Performance of deep-submicrometer very large scale integrated (VLSI) circuits is being increasingly dominated by the interconnects due to decreasing wire pitch and increasing die size.  ...  A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for  ...  Hutchby of SRC for providing initial seed funding and A. Mehrotra, University of Illinois at Urbana-Champaign, for several technical discussions during the initial phase of this project.  ... 
doi:10.1109/5.929647 fatcat:ibkenr5mvrcn3cwc4mxsnpnbwy

On the Applicability of Single-Walled Carbon Nanotubes as VLSI Interconnects

N. Srivastava, Hong Li, F. Kreupl, K. Banerjee
2009 IEEE transactions on nanotechnology  
The applicability of carbon nanotube (CNT) based vias (vertical interconnects)-the most realizable CNT interconnects in the current state of the artis addressed for the first time.  ...  of SWCNT bundles for realistic very large scale integration (VLSI) interconnect dimensions, and a quantitative evaluation of the importance of inductive effects in SWCNT interconnects are presented.  ...  Equivalent Circuit Model for SWCNT Bundle Interconnect Delay The equivalent circuit model for an SWCNT bundle interconnect is shown in Fig. 17 .  ... 
doi:10.1109/tnano.2009.2013945 fatcat:64zwio4jkrddfpe2tk7yatggda

High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design

Hong Li, Kaustav Banerjee
2009 IEEE Transactions on Electron Devices  
1 Significant frequency (fs) is the highest frequency in the frequency spectrum of a signal pulse up to which the amplitudes of the corresponding frequency components are significant.  ...  Skin depth and interconnect parasitics (resistance and inductance) are also extracted at the significant frequency. 0018-9383/$26.00  ...  For example, the growth temperature of CNT via has been recently lowered to 365 • C, and with this low temperature growth, the integration of CNT via structure in ultralow k dielectric (k = 2.6) with good  ... 
doi:10.1109/ted.2009.2028395 fatcat:z36zck2k6zakbai6hlvbhjyxye

Analog VLSI-Based Modeling of the Primate Oculomotor System

Timothy K. Horiuchi, Christof Koch
1999 Neural Computation  
It is driven by two different analog VLSI chips, one mimicking cortical visual processing for target selection and tracking and another modeling brain stem circuits that drive the eye muscles.  ...  Analog very large-scale integrated (VLSI) electronic circuit technology provides such an enabling technology.  ...  Acknowledgments We thank Brooks Bishofberger for mechanical design of the oculomotor system and fabrication of some of the dynamics simulation electronics, Tobi Delbrück for advice on photoreceptor circuit  ... 
doi:10.1162/089976699300016908 pmid:9950732 fatcat:yljsnhiwgzegrdl23ffo4fkcx4

Multiple Si layer ICs

Shukri J. Souri, Kaustav Banerjee, Amit Mehrotra, Krishna C. Saraswat
2000 Proceedings of the 37th conference on Design automation - DAC '00  
Continuous scaling of VLSI circuits is reducing gate delays but rapidly increasing interconnect delays.  ...  Finally, implications of 3-D architecture on several circuit designs are also discussed.  ...  Acknowledgements This work was supported by the DARPA AME Program and the MARCO Interconnect Technology Focus Center at Stanford University. References  ... 
doi:10.1145/337292.337394 dblp:conf/dac/SouriBMS00 fatcat:5w4ly4yharaybi4nztrishl7xa

High-reliability fault tolerant digital systems in nanometric technologies: Characterization and design methodologies

C. Bolchini, A. Miele, C. Sandionigi, M. Ottavi, S. Pontarelli, A. Salsano, C. Metra, M. Omana, D. Rossi, M. Sonza Reorda, L. Sterpone, M. Violante (+3 others)
2012 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)  
Ottavi is funded by the Italian Ministry for University and Research; Program "Incentivazione alla mobilità di studiosi stranieri e italiani residenti all'estero", D.M. n.96, 23.04.2001  ...  PROJECT GOAL While the shrinking of minimum dimensions of integrated circuits till tenths of nanometers allows the integration of millions of gates on the single chip, it also implies the growth of the  ...  The second method uses a hash-based probabilistic structure called "Bloom filter" to check the correctness of CAM results [26] .  ... 
doi:10.1109/dft.2012.6378211 dblp:conf/dft/BolchiniMSOPSMORRSVGBP12 fatcat:ezmwp45dh5htjha3kzjhbanfra

Double-gate fully-depleted SOI transistors for low-power high-performance nano-scale circuit design

Rongtian Zhang, Kaushik Roy, David Janes
2001 Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01  
This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance.  ...  Double-gate fully-depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits.  ...  It is, therefore, necessary to look for new device structures to sustain the growth of the VLSI industry in the nano-scale generations.  ... 
doi:10.1145/383082.383136 dblp:conf/islped/ZhangRJ01 fatcat:d6ahveya7ja6dgudzigk5f7vqy

Low-power high-performance double-gate fully depleted SOI circuit design

Rongtian Zhang, K. Roy
2002 IEEE Transactions on Electron Devices  
This paper investigates the impact of scaling on the demand and challenges of DGFD SOI circuit design for low power and high performance.  ...  Double-gate fully depleted (DGFD) SOI circuits are regarded as the next generation VLSI circuits.  ...  It is therefore, necessary to look for new device structures to sustain the growth of the VLSI industry in the nanoscale generations.  ... 
doi:10.1109/16.998595 fatcat:bogwbikxdvf2th5ynuzfkiu4ci

Why mechanical design cannot be like VLSI design

Daniel E. Whitney
1996 Research in Engineering Design  
This paper argues that there are fundamental reasons, that is, reasons based on natural phenomena, that keep mechanical design from approaching the ideal of VLSI design methods.  ...  It is widely agreed that the design methods and computer support of VLSI design are generally more mature than those of mechanical items.  ...  Two kinds of models are made: circuit performance models and geometric models. The circuit models cover electrical, timing, and heat factors.  ... 
doi:10.1007/bf01608348 fatcat:kxnfmc476nafpo2blepcgiuhuq

Carbon Nanotube Vias: Does Ballistic Electron–Phonon Transport Imply Improved Performance and Reliability?

Hong Li, Navin Srivastava, Jun-Fa Mao, Wen-Yan Yin, Kaustav Banerjee
2011 IEEE Transactions on Electron Devices  
Accurate resistance and thermal conductance models are provided for isolated CNTs, as well as bundles of these, based on detailed electrical and thermal transport physics in the submicrometer regime.  ...  While the large resistance of CNT vias may not be a significant concern for local interconnects, the resistance must be minimized to avoid degradation of global interconnect performance.  ...  modeling the performance of CNT interconnects in VLSI circuits have focused on the horizontal wires [3] , [8] - [13] .  ... 
doi:10.1109/ted.2011.2157825 fatcat:myyc5ou2zrgfvbgh56ybuep6ha

[Back cover]

1986 IEEE Electron Device Letters  
Its aim 1s to bring together designers, producers, and users of custom ICs to discuss recent developments and future directions I n custom integrated circuits.  ...  The CICC '87 is sponsored by the IEEE Electron Devices Society, the IEEE Solid-state Circuits Council, and co-sponsored by the IEEE Rochester Section.  ...  ., + , EDL Apr 862 1 1-2 13 temperature dependence of latchup in VLSI CMOS structures. gates for VLSI applications.  ... 
doi:10.1109/edl.1986.26528 fatcat:j4qwskixlfb6fmipfzr3d7geui

Memory-span concepts and the synthesis of sequential machines in feedback shift-register form

Robert L. Martin
1967 8th Annual Symposium on Switching and Automata Theory (SWAT 1967)  
Defect Tolerance in VLSI Circuits Manufacturing Defects and Circuit Faults; Probability of Failure and Critical Areas; Basic Yield Models; Yield Enhancement through Redundancy.  ...  of VLSI circuit design technology; Complex systems design and processors; Design process in embedded system.  ...  Mobile Operating Systems Operating System, PalmOS, Windows CE, Symbian OS, Linux for Mobile Devices.  ... 
doi:10.1109/focs.1967.19 dblp:conf/focs/Martin67 fatcat:fwn5xjv7mbcsja5xrhcmdo6ipe
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