Filters








30 Hits in 3.1 sec

Efficient circuit clustering for area and power reduction in FPGAs

Amit Singh, Ganapathy Parthasarathy, Malgorzata Marek-Sadowska
2002 ACM Transactions on Design Automation of Electronic Systems  
Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability.  ...  Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented.  ...  Rent's rule is an empirical metric used to quantify circuit complexity.  ... 
doi:10.1145/605440.605448 fatcat:6f6va6hcwrgorpi5zg2e4s3ddu

Efficient circuit clustering for area and power reduction in FPGAs

Amit Singh, Malgorzata Marek-Sadowska
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability.  ...  Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented.  ...  Rent's rule is an empirical metric used to quantify circuit complexity.  ... 
doi:10.1145/503048.503058 dblp:conf/fpga/SinghM02 fatcat:kskckeh5cfcbzdi2vncrk4ysoa

Efficient circuit clustering for area and power reduction in FPGAs

Amit Singh, Malgorzata Marek-Sadowska
2002 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays - FPGA '02  
Effective seed selection, coupled with an interconnect-resource aware clustering and placement, can have a favorable impact on circuit routability.  ...  Power dissipation simulations using a buffered pass-transistor-based FPGA interconnect model are presented.  ...  Rent's rule is an empirical metric used to quantify circuit complexity.  ... 
doi:10.1145/503057.503058 fatcat:mhotmkr7znatxb754pj3i7ndwa

Automatic Partitioning for Improved Placement and Routing in Complex Programmable Logic Devices [chapter]

Valavan Manohararajah, Terry Borer, Stephen D. Brown, Zvonko Vranesic
2002 Lecture Notes in Computer Science  
The resulting partitions are then placed using an enhanced placement tool.  ...  A novel algorithm based on Rent's rule and simulated annealing partitions a design before it enters the place and route stage in CPLD CAD.  ...  Recently, Rent's rule has found several uses in interconnection prediction and congestion estimation during placement [11] [12] [13] [14] .  ... 
doi:10.1007/3-540-46117-5_25 fatcat:vo4au7osm5dzzcay7qcntb66zi

A Synthesis Approach for Coarse-Grained Antifuse-Based FPGAs

Chang Woo Kang, Ali Iranli, Massoud Pedram
2007 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
Given this minimum number of macro logic cells, we introduce an interconnect-aware clustering algorithm that assigns logic cells to individual macro cells so as to minimize the routing costs.  ...  In this paper, we present a synthesis technique targeted toward coarse-grained, antifuse-based FPGAs. A macro logic cell, in this class of FPGAs, has multiple inputs and multiple outputs.  ...  It alleviates routing congestion for clustered FPGAs by absorbing as many small nets into clusters as possible, and depopulating clusters according to Rent's rule in order to achieve spatial uniformity  ... 
doi:10.1109/tcad.2007.895781 fatcat:jcmpia6pencvhnmgfficillfme

Methodology for early estimation of hierarchical routing resources in 3D FPGAs

Krishna Chaitanya Nunna, Farhad Mehdipour, Masayoshi Yoshimura, Kazuaki Murakami
2012 2012 IEEE/IFIP 20th International Conference on VLSI and System-on-Chip (VLSI-SoC)  
ACKNOWLEDGEMENT The authors wish to thank Koji Inoue, Lovic Gauthier (Kyushu University, Japan), Antoine Trouve (ISIT, Fukuoka) and Nobuaki Miyakawa (Honda Research Institute, Japan) for their useful comments  ...  He derived the model by satisfying the Rent's rule [15] . In his work, Stroobandt first partitions the given circuit and the 3D Manhattan grid into equal parts.  ...  In conjunction with reducing FPGA power, efficient power-aware design will require new estimation tools that gauge power dissipation at the early stages of the design process.  ... 
doi:10.1109/vlsi-soc.2012.7332103 fatcat:ghmfwtvzrfdophjgqv5xpjdz34

Architecture-specific packing for virtex-5 FPGAs

Taneem Ahmed, Paul D. Kundarewich, Jason H. Anderson, Brad L. Taylor, Rajat Aggarwal
2008 Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays - FPGA '08  
The second LUT output is associated with slower speed, and therefore, must be used judiciously.  ...  We consider packing in the commercial FPGA context and examine the speed, performance and power trade-offs associated with packing in a state-of-the art FPGA -the Xilinx R Virtex TM -5 FPGA.  ...  Rent's rule was used to establish a preference for how many logic block inputs should be used during packing, leading to lower overall interconnect usage, capacitance and power.  ... 
doi:10.1145/1344671.1344675 dblp:conf/fpga/AhmedKATA08 fatcat:ptwkqofa7vc7lhlx6uo4y5k6iu

Packing Techniques for Virtex-5 FPGAs

Taneem Ahmed, Paul D. Kundarewich, Jason H. Anderson
2009 ACM Transactions on Reconfigurable Technology and Systems  
Packing is a key step in the FPGA tool flow that straddles the boundaries between synthesis, technology mapping and placement.  ...  The second LUT output has reduced speed, and therefore, must be used judiciously.  ...  An entirely different approach for power-driven packing was shown in Singh and Marek-Sadowska [2002] , where Rent's rule was used to establish a preference for how many logic block inputs should be used  ... 
doi:10.1145/1575774.1575777 fatcat:mrcwkvhzi5hdjkcg6bxu7iecue

Three-dimensional Integrated Circuits: Design, EDA, and Architecture

Guangyu Sun
2011 Foundations and Trends® in Electronic Design Automation  
using CMOS technology.  ...  This approach processes each layer separately, using conventional fabrication techniques. These multiple layers are then assembled to build up 3D IC, using bonding technology.  ...  Rule [126] describing the relationship between the interconnect count (X) and the gate count (N gate ) can be used.  ... 
doi:10.1561/1000000016 fatcat:usmthkco4rfavmnlvvmmgxolcq

Very Large Scale Spatial Computing [chapter]

André DeHon
2002 Lecture Notes in Computer Science  
A natural consequence is that the dominant effects which govern our computing space change from the total number of operations and temporal locality to interconnect complexity and spatial locality.  ...  This is the traditional domain of placement and can reduce wiring requirements from the O(N 2 ) area identified above to O(N 2p ) [5] , where p is the exponent in Rent's Rule [16] and typically has  ...  As capacity has grown, programmable spatial designs have become increasingly practical using Field-Programmable Gate-Arrays (FPGAs).  ... 
doi:10.1007/3-540-45833-6_3 fatcat:bpdt7mr6ofbvzayatkvduybpzi

An End-to-End Tool Flow for FPGA-Accelerated Scientific Computing

Greg Stitt, Alan George, Herman Lam, Melissa Smith, Vikas Aggarwal, Gongyu Wang, Casey Reardon, Brian Holland, Seth Koehler, James Coole
2011 IEEE Design & Test of Computers  
The details are outside the scope of this article, but the basic approach combines the critical-path delay of individual cores with an analysis based on Rent's rule to estimate effects of routing congestion  ...  Despite these advantages, FPGA use has been limited by significantly increased application design complexity as compared to software design, which is mainly due to RTL design challenges.  ... 
doi:10.1109/mdt.2011.46 fatcat:3ganqjg75jh3nanzr6obzc4xqq

Field-Programmable Wiring Systems

Victor Murray, Marios Pattichis, Daniel Llamocca, James Lyke
2015 Proceedings of the IEEE  
Generally, field-programmable wiring systems support the use of multidomain fabrics that can be used to route analog, power, digital signals, optical, microwave signals, etc.  ...  ABSTRACT | Field-programmable wiring systems refer to methods and hardware that can maintain the interconnection of components of different types.  ...  The effect of Rent's rule [39] on architecture has been extensively discussed [40] for FPGA design.  ... 
doi:10.1109/jproc.2015.2432123 fatcat:3eofp57jkvhqxohggjfig3jaqe

A power-aware algorithm for the design of reconfigurable hardware during high level placement

Wing On Fung, Tughrul Arslan, M.Gh. Negoita, T. Arslan
2008 Journal of Knowledge-based & Intelligent Engineering Systems  
The proposed system modeled the number of switches used in the circuit and employed simulated annealing algorithm to reduce the overall routing power.  ...  This paper looks at the CAD design process of reconfigurable devices and presents a novel method to gain power savings during the placement stage of the CAD flow.  ...  Net-driven [5, 6] timing placement on the other hand is less complex and can be more efficient.  ... 
doi:10.3233/kes-2008-12306 fatcat:2btup7zvtnbufccvfmh25qca7q

A Power-Aware Algorithm for the Design of Reconfigurable Hardware during High Level Placement

Wing On Fung, T. Arslan
2007 Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)  
The proposed system modeled the number of switches used in the circuit and employed simulated annealing algorithm to reduce the overall routing power.  ...  This paper looks at the CAD design process of reconfigurable devices and presents a novel method to gain power savings during the placement stage of the CAD flow.  ...  Net-driven [5, 6] timing placement on the other hand is less complex and can be more efficient.  ... 
doi:10.1109/ahs.2007.15 dblp:conf/ahs/FungA07 fatcat:medweajdlvavxmbvhmhsffb2ye

On the asymptotic costs of multiplexer-based reconfigurability

Johnathan York, Derek Chiou
2012 Proceedings of the 49th Annual Design Automation Conference on - DAC '12  
The specific approach, based upon Rent's rule [20] , is well known in the EDA community [6] and has proved useful in quantifying circuit characteristics in order to estimate features including wirelength  ...  In another paper, the datapath merging technique (including a novel Ant Colony Optimization algorithm) is used to generate placement constraints to force the FPGA synthesis tool to place similar logic  ... 
doi:10.1145/2228360.2228503 dblp:conf/dac/YorkC12 fatcat:hjljrhriuzabtjawbpgrpjc5hm
« Previous Showing results 1 — 15 out of 30 results