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Communication Synthesis for Interconnect Minimization Targeting Distributed Register-File Microarchitecture

Juinn-Dar HUANG, Chia-I CHEN, Yen-Ting LIN, Wan-Ling HSU
2011 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
The experimental results show that up to 24.7% and 12.7% reduction on IIC and latency can be achieved respectively as compared to the previous work. key words: communication synthesis, distributed register-file  ...  In this article, we propose a new resourceconstrained communication synthesis algorithm for optimizing both interisland connections (IICs) and latency targeting on distributed registerfile microarchitecture  ...  The distributed register-file microarchitecture (DRFM) is one of the DR-based architectures and is recently proposed in [6] , [7] , which takes full advantage of those platforms with a rich set of distributed  ... 
doi:10.1587/transfun.e94.a.1151 fatcat:2wem74t6fnecdeiz4bpiiylkry

Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family

Chia-I Chen, Juinn-Dar Huang
2011 2011 IEEE Computer Society Annual Symposium on VLSI  
Proposed Architecture Here we propose a new microarchitecture -distributed register-file microarchitecture with inter-island delay (DRFM-IID).  ...  The distributed register-file microarchitecture (DRFM) is one of the DR-based architectures and is recently proposed in [4] , which takes full advantage of those platforms with a rich set of distributed  ... 
doi:10.1109/isvlsi.2011.19 dblp:conf/isvlsi/ChenH11 fatcat:mj5kpnliejarvd7cmdxga2kbnm

Architecture and Synthesis for On-Chip Multicycle Communication

J. Cong, Y. Fan, G. Han, X. Yang, Z. Zhang
2004 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  
In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication.  ...  On top of the RDR microarchitecture, novel layout-driven architectural synthesis algorithms have been developed for multicycle communication, including scheduling-driven placement, placement-driven simultaneous  ...  Potkonjak of the University of California, Los Angeles, for sharing benchmarks, Professor K. Choi of Seoul National University, Seoul, Korea, for providing the CDFG toolkit [35] , and Dr. V.  ... 
doi:10.1109/tcad.2004.825872 fatcat:q3jbmcmtz5g2lccyfz2lirpzqa

Platform-based resource binding using a distributed register-file microarchitecture

Jason Cong, Yiping Fan, Wei Jiang
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files  ...  DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms.  ...  With a similar insight in mind, we present a distributed register-file microarchitecture (DRFM) for resource binding in behavior synthesis.  ... 
doi:10.1145/1233501.1233648 dblp:conf/iccad/CongFJ06 fatcat:wms6qu5c7ncffkyi43oefylq6e

Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture

Jason Cong, Yiping Fan, Wei Jiang
2006 Computer-Aided Design (ICCAD), IEEE International Conference on  
This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files  ...  DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms.  ...  With a similar insight in mind, we present a distributed register-file microarchitecture (DRFM) for resource binding in behavior synthesis.  ... 
doi:10.1109/iccad.2006.320017 fatcat:ibm27inr4bd6zkaojkgdtjsylu

Performance-Driven Architectural Synthesis for Distributed Register-File Microarchitecture with Inter-Island Delay

Juinn-Dar HUANG, Chia-I CHEN, Wan-Ling HSU, Yen-Ting LIN, Jing-Yang JOU
2012 IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences  
In this article, we propose the distributed register-file microarchitecture with inter-island delay (DRFM-IID).  ...  architectural synthesis for better optimization outcomes.  ...  The distributed register-file microarchitecture (DRFM) is one of the DR-based architectures and is recently proposed in [14] , [15] .  ... 
doi:10.1587/transfun.e95.a.559 fatcat:o53fb6cenbekbe4teun4cxphdm

Simultaneous resource binding and interconnection optimization based on a distributed register-file microarchitecture

Jason Cong, Yiping Fan, Junjuan Xu
2009 ACM Transactions on Design Automation of Electronic Systems  
This paper presents a platform-based resource binding approach based on a distributed register-file microarchitecture (DRFM), which makes efficient use of distributed embedded memory blocks as register  ...  DRFM provides a useful architectural template and a direct optimization objective for minimizing inter-island connections for synthesis algorithms.  ...  With a similar insight in mind, we present a distributed register-file microarchitecture (DRFM) for resource binding in behavior synthesis.  ... 
doi:10.1145/1529255.1529257 fatcat:pipnwrgrdbaivpw2hxub62w6gq

A Signature-Based Power Model for MPSoC on FPGA

Roberta Piscitelli, Andy D. Pimentel
2012 VLSI design (Print)  
We integrated the power estimation technique in a system-level MPSoC synthesis framework.  ...  The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power  ...  We would like to give special credits to Todor Stefanov and Mohamed Bamakhrama for their support on implementing the MicroBlaze software driver for the PMBus controller.  ... 
doi:10.1155/2012/196984 fatcat:77remrhkjzhk3gjj3y7hiigz5e

Issues and Challenges in Development of Massively-Parallel Heterogeneous MPSoCs Based on Adaptable ASIPs

Lech Jozwiak, Menno Lindwer
2011 2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing  
This paper focuses on mastering the automatic architecture synthesis and application mapping for heterogeneous massively-parallel MPSoCs based on customizable application-specific instruction-set processors  ...  of MPSoCs for embedded applications.  ...  slots into clusters, number of register files, ports and registers, interconnects between clusters, to name some of them.  ... 
doi:10.1109/pdp.2011.55 dblp:conf/pdp/JozwiakL11 fatcat:s7hkhc7gx5bhtnarwpquhwvc5m

Platform-Based Behavior-Level and System-Level Synthesis

Jason Cong, Yiping Fan, Guoling Han, Wei Jiang, Zhiru Zhang
2006 2006 IEEE International SOC Conference  
With the rapid increase of complexity in Systemon-a-Chip (SoC) design, the electronic design automation (EDA) community is moving from RTL (Register Transfer Level) synthesis to behavioral-level and system-level  ...  the logic, interconnects, performance, and power simultaneously.  ...  , Magma Design Automation, Inc., and Xilinx, Inc. under the California MICRO program.  ... 
doi:10.1109/socc.2006.283880 dblp:conf/socc/CongFHJZ06 fatcat:yupmpajpw5ec7lertm6uqxy2ne

Architecture-level synthesis for automatic interconnect pipelining

Jason Cong, Yiping Fan, Zhiru Zhang
2004 Proceedings of the 41st annual conference on Design automation - DAC '04  
Specifically, we extend the recently proposed Regular Distributed Register (RDR) micro-architecture to support interconnect pipelining.  ...  We formulate a novel global interconnect sharing problem for global wiring minimization and show that it is polynomial time solvable by transformation to a special case of the real-time scheduling problem  ...  The authors thank the anonymous reviewers of [6] and [7] for pointing out the wiring overhead problem associated with the RDR architecture, and Dr.  ... 
doi:10.1145/996566.996731 dblp:conf/dac/CongFZ04 fatcat:u4gmoclngfcn5fynv3yhrtvera

Performance-driven architectural synthesis for distributed register-file microarchitecture considering inter-island delay

Juinn-Dar Huang, Chia-I Chen, Wan-Ling Hsu, Yen-Ting Lin, Jing-Yang Jou
2010 Proceedings of 2010 International Symposium on VLSI Design, Automation and Test  
A distributed register-file microarchitecture with inter-island delay (DRFM-IID), proposed in this thesis, is one of the DR-based architectures.  ...  Several distributed register (DR) architectures are proposed to cope with this problem by keeping most wires local.  ...  Distributed register-file microarchitecture (DRFM) is one of the DR-based architectures and is recently proposed in [9] .  ... 
doi:10.1109/vdat.2010.5496717 fatcat:dwvym2gtyrcyhog5n23yxmurma

A proposed synthesis method for Application-Specific Instruction Set Processors

Péter Horváth, Gábor Hosszú, Ferenc Kovács
2015 Microelectronics Journal  
The new solution is based on a novel abstract ASIP model and a modeling language (Algorithmic Microarchitecture Description Language, AMDL) optimized for this architecture model.  ...  Contrary to this, the final register-transfer level models are usually created, at least partly, manually. This paper presents a novel approach for automated hardware model generation for ASIPs.  ...  Acknowledgment The work reported in the paper has been developed in the framework of the project "Talent care and cultivation in the scientific workshops of BME".  ... 
doi:10.1016/j.mejo.2015.01.001 fatcat:6gu6fd2stnbpvcpfugaku3cnje

Computer aided design of fault-tolerant application specific programmable processors

M. Potkonjak, K. Kim, R. Karri
2000 IEEE transactions on computers  
ASPP fault tolerance constraints are incorporated during scheduling, allocation, and assignment phases of behavioral synthesis.  ...  We address each of them and demonstrate the effectiveness of the overall approach, the synthesis algorithms, and software implementations on a number of industrial-strength designs.  ...  The sources of the overhead are 1) the increased interconnect requirements and 2) the coefficient registers in the current dedicated register file hardware model.  ... 
doi:10.1109/12.895942 fatcat:2aaeuskl4zbw3emjcaehhmihty

Intel nehalem processor core made FPGA synthesizable

Graham Schelle, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang, Jamison Collins, Ethan Schuchman, Perrry Wang, Xiang Zou, Gautham Chinya, Ralf Plate (+2 others)
2010 Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays - FPGA '10  
We present a FPGA-synthesizable version of the Intel Nehalem processor core, synthesized, partitioned and mapped to a multi-FPGA emulation system consisting of Xilinx Virtex-4 and Virtex-5 FPGAs.  ...  The synthesizable Nehalem core is able to boot Linux and execute standard x86 workloads with all architectural features enabled.  ...  Ketan Paranjape for the productive collaboration, guidance and support throughout the project.  ... 
doi:10.1145/1723112.1723116 dblp:conf/fpga/SchelleCSWZCPMOHSBSW10 fatcat:rim6adpnardmdptcchem5y3d2q
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