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Corona: Ring-based interconnected topology for on-chip network

Maryam Bahmani, Midia Reshadi, Ahmad Khademzadeh, Akram Reza
2008 2008 3rd International Design and Test Workshop  
In this paper we present the basic ideas behind the development of our novel ring based Network-on-Chip (NoC) architecture, called "Corona".  ...  Also, the power consumption is reduced averagely in Corona in comparison to 2D mesh 21% and 29% for localized and non-localized traffic scenarios.  ...  Due to this, Network on Chip has been presented to solve these problems as a packet-based on chip communication networks [3] [4] [5] .  ... 
doi:10.1109/idt.2008.4802497 fatcat:ckhifiqu4jfv7lvuknb5xhouta

A Hybrid Interconnect Network-on-Chip and a Transaction Level Modeling Approach for Reconfigurable Computing

Thomas Lenart, Henrik Svensson, Viktor Öwall
2008 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008)  
This paper presents a hybrid interconnect network consisting of a local network with dedicated wires and a global hierarchical network.  ...  In contrast, the Network-On-Chip (NoC) concept propose highly flexible interconnect topologies based on intelligent routing networks, where any two nodes in the system can initiate communication without  ...  the interconnect network.  ... 
doi:10.1109/delta.2008.85 dblp:conf/delta/LenartSO08 fatcat:tnew6flmgnfgvaxtofzpe4g2zm

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

E. Cota, F.L. Kastensmidt, M. Cassel, M. Herve, P. Meirelles, A. Amory, M. Lubaszewski
2008 IEEE transactions on computers  
A novel strategy for detecting interconnect faults between distinct channels in networks-on-chip is proposed.  ...  Short faults between distinct channels in the data, control, and communication handshake wires are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.  ...  A solution for such a communication bottleneck is the use of an embedded switching network, called Network-on-Chip (NoC), to interconnect the IP modules in SoCs [2] .  ... 
doi:10.1109/tc.2008.62 fatcat:cumfugwfnzaprfftua25dqphgm

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism

A.M. Amory, K. Goossens, E.J. Marinissen, M. Lubaszewski, F. Moraes
2007 IET Computers & Digital Techniques  
.: 'Wrapper design for the reuse of networks-on-chip as test access mechanism.'  ...  The new wrapper design allows a functional interconnect, such as an on-chip bus or network-on-chip (NOC) to transport test data to embedded cores, and hence eliminates the need for a conventional dedicated  ...  Multi-bus solutions have provided a temporary alleviation, but for the longer-term, a scalable solution is a network-on-chip (NOC) [4] [5] [6] [7] .  ... 
doi:10.1049/iet-cdt:20060152 fatcat:6uqz2hzbbrfwvoozjkpmj6taiy

BIST for Network-on-Chip Interconnect Infrastructures

C. Grecu, P. Pande, A. Ivanov, R. Saleh
24th IEEE VLSI Test Symposium  
In this paper, we present a novel built-in self-test methodology for testing the inter-switch links of network-on-chip (NoC) based chips.  ...  This methodology uses a high-level fault model that accounts for crosstalk effects due to inter-wire coupling.  ...  Chemla of L'Ecole Politechnique Universitaire de Marseille for help with simulations. References  ... 
doi:10.1109/vts.2006.22 dblp:conf/vts/GrecuPIS06 fatcat:mkoecyd65vc3xl2r4wojfnvgiq

Leakage-Aware Interconnect for On-Chip Network

Yuh-Fang Tsai, V. Narayaynan, Yuan Xie, M.J. Irwin
Design, Automation and Test in Europe  
On-chip networks have been proposed as the interconnect fabric for future systems-on-chip and multi-processors on chip.  ...  Power is one of the main constraints of these systems and interconnect consumes a significant portion of the power budget.  ...  CONCLUSIONS As existing interconnect designs in on-chip network draws significant leakage power, we proposed several dual-V t designs to reduce both active and standby leakage.  ... 
doi:10.1109/date.2005.195 dblp:conf/date/TsaiVXI05 fatcat:puiblavujfd3biywphjanij2di

A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips

W.-D. Weber, J. Chou, I. Swarbrick, D. Wingard
Design, Automation and Test in Europe  
However, the known solutions for off-chip interconnects such as large-scale networks are not necessarily applicable to the on-chip environment.  ...  Latency and memory constraints for on-chip interconnects are quite different from largerscale interconnects. This paper introduces a novel on-chip interconnect arbitration scheme.  ...  CPU MIPS Work focussed on quality-of-service specifically for on-chip interconnects is much sparser and more recent.  ... 
doi:10.1109/date.2005.33 dblp:conf/date/WeberCSW05 fatcat:jinrp4cd2jemfe3dlbwkx4bngi

Microwave model of anisotropic conductive film flip-chip interconnections for high frequency applications

Myung-Jin Yim, Woonghwan Ryu, Young-Doo Jeon, Junho Lee, Seungyoung Ahn, Joungho Kim, Kyung-Wook Paik
1999 IEEE transactions on components and packaging technologies  
As flip chip bumps, electroless Ni/Au plating was performed on Al input/output (I/O) pads of test IC chips.  ...  The same measurements and conversion were conducted on the test chip mounted substrates at the same frequency range.  ...  Fig. 7 . 7 Extraction procedure for the ACF flip-chip interconnection model parameters from the S-parameter measurements and microwave network analysis.  ... 
doi:10.1109/6144.814974 fatcat:xghk7wmr5nb7pomxitca6h6noa

Guest Editors' Introduction: Tackling Key Problems in NoCs

Yatin Hoskote, Radu Marculescu, Li-Shiuan Peh
2008 IEEE Design & Test of Computers  
Her research interests include on-chip networks, many-core architectures, and low-power interconnection networks.  ...  This new paradigm places multiple cores on the same die and connects them through an on-die interconnect, effectively building a network on a chip.  ... 
doi:10.1109/mdt.2008.141 fatcat:by25vkyvb5dujpp2deb44oluwe

Guest Editors' Introduction

Edoardo Fusella, Mahdi Nikdast, Ian O'Connor, José Flich, Sudeep Pasricha
2019 ACM Journal on Emerging Technologies in Computing Systems  
Spare Core Placement," (5) "Thermal-Aware Test Scheduling Strategy for Network-on-Chip-Based Systems," (6) "PANE: Pluggable Asynchronous Network-on-Chip Simulator," and ( 7 ) "BigBus: A Scalable Optical  ...  In the next article, "Thermal-Aware Test Scheduling Strategy for Network-on-Chip-Based Systems," Kanchan et al. present a preemptive test scheduling technique to improve the test time by reducing resource  ... 
doi:10.1145/3296021 fatcat:eyv5pf6fwncqhoiyvhgxctuhbe

Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies

Partha Pratim Pande, Sriram Vangal
2010 IEEE Design & Test of Computers  
We thank Design & Test editor-in-chief Krishnendu Chakrabarty for supporting us, and Tim Cheng, D&T editor in chief emeritus, under whose leadership we actually started the groundwork for this special  ...  His current research interests are novel interconnect architectures  ...  The last article, ''Global On-Chip Coordination at Light Speed'' by Zheng Li et al., proposes a design of a photonic on-chip network for many-core systems.  ... 
doi:10.1109/mdt.2010.87 fatcat:q6brfi3ggvhllok2zdp2n3kwau

Chip-Package Hybrid Clock Distribution Network and DLL for Low Jitter Clock Delivery

D. Chung, C. Ryu, H. Kim, C. Lee, J. Kim, K. Bae, J. Yu, H. Yoo, J. Kim
2006 IEEE Journal of Solid-State Circuits  
The proposed hybrid clock distribution network and DLL provide digital noise-free and low-jitter clock signals by utilizing lossless package layer interconnections instead of lossy on-chip global wires  ...  The lossless package layer interconnections become high-frequency waveguides and provide a repeater-free clock distribution network; thus, the clock signal becomes free of on-chip power supply noise.  ...  The chip-package hybrid design scheme still requires on-chip interconnections for wafer-level tests.  ... 
doi:10.1109/jssc.2005.859882 fatcat:gmc46jyjirhkfnkgc26h6rqm24

Design, Synthesis, and Test of Networks on Chips

P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, G. De Micheli
2005 IEEE Design & Test of Computers  
The micronetwork must ensure energy efficiency and quality-of-service (QoS) requirements such as relia- Design, Synthesis, and Test of Networks on Chips Editor's note: For networks on chips to succeed  ...  The On-Chip Communication Network (OCCN) project 8 proposes an efficient, opensource research and development framework for the specification, modeling, and simulation of on-chip communication architectures  ... 
doi:10.1109/mdt.2005.108 fatcat:ftg32fzp2jelppgskbqb34ehiy

Interconnection Generation for System-on-Chip Design

Markus Winter, Gerhard Fettweis
2006 2006 International Symposium on System-on-Chip  
In recent years interconnection architectures for system-on-chip (SoC) design have been subject of intense research.  ...  The architectures range from clustered bus based systems to packetswitched network-on-chips. Thereby, the application of these architectures to systems should not be done by hand but automated.  ...  Therefore, network behavior must be tested for all assumable cases of access from modules. It is impossible to do this for every system-on-chip again.  ... 
doi:10.1109/issoc.2006.321975 dblp:conf/issoc/WinterF06 fatcat:r35b3lrzjrecrk4wxmjaub6nli

The network is the chip

G. Martin
2005 IEEE Design & Test of Computers  
"the network is my post office, my map, my stereo system, my photo album ..." and so on.  ...  With the growth in cell phones, digital cameras, portable music players, wireless e-mail, GPS sensors, and automotive map displays that rely on wired and wireless networks, you might be tempted to say  ...  on-chip buses to on-chip networks, and arbitration and routing schemes for on-chip packet networks.  ... 
doi:10.1109/mdt.2005.48 fatcat:qhq6irfgcbh2jpvbvljpnne5uy
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