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Intellectual Property Protection for Integrated Systems Using Soft Physical Hash Functions [chapter]

François Durvaux, Benoît Gérard, Stéphanie Kerckhof, François Koeune, François-Xavier Standaert
2012 Lecture Notes in Computer Science  
Intellectual property right violations are an important problem for integrated system designers. We propose a new solution for mitigating such violations, denoted as soft physical hash functions.  ...  For this purpose, we first introduce and formalize the components of an intellectual property detection infrastructure using soft physical hash functions.  ...  Standaert is a Research Associate of the Belgian Fund for Scientic Research (FNRS-F.R.S).  ... 
doi:10.1007/978-3-642-35416-8_15 fatcat:f24sz2bitjbhvbsx37ixirgati

A Flexible Design Flow for Software IP Binding in FPGA

Michael A. Gora, Abhranil Maiti, Patrick Schaumont
2010 IEEE Transactions on Industrial Informatics  
Index Terms-Design flow, firmware, field programmable gate arrays (FPGA), intellectual property, physical unclonable function, secure embedded systems, security, software binding.  ...  We accomplish this by leveraging the qualities of a Physical Unclonable Function (PUF) and a tight integration of hardware and software security features.  ...  Physical Unclonable Function (PUF) For our prototype implementation, we used an RO-based PUF that has been proposed in [1] using several identical ROs.  ... 
doi:10.1109/tii.2010.2068303 fatcat:uqp4j6jztjag7koa7mvid3t37q

A flexible design flow for software IP binding in commodity FPGA

Michael A. Gora, Abhranil Maiti, Patrick Schaumont
2009 2009 IEEE International Symposium on Industrial Embedded Systems  
Software intellectual property (SWIP) is a critical component of increasingly complex FPGA based system on chip (SOC) designs.  ...  $25.00 ©2009 IEEE 211 SIES 2009 Authorized licensed use limited to: to IEEExplore provided by Virginia Tech Libraries.  ...  Hardware intellectual property (HWIP) in an FPGA-based system can be protected using bitstream encryption provided by FPGA manufacturers.  ... 
doi:10.1109/sies.2009.5196217 dblp:conf/sies/GoraMS09 fatcat:ya2do63yj5b5pk5gkeworkeomq

USB Key Based Antipiracy Solution

Manjiri R. Bawane, Madhavi S. Borkar, Payal R. Wawarkar, Sanika M. Shende, Heena K. Chandel, Ketki R. Bhakare
2015 Journal of advance research in computer science & enigneering  
USBkey is a new kind of intelligent security product that comprises microprocessor and operation system. Computer software is intellectual property, and is protected by copyright law.  ...  A hardware based system consist of physical device and hence cannot be shared over the internet and hence eliminates the flaws of conventional mechanisms discussed above.  ...  One important technique is integrity-checking which use self-hashing to check the integrity of the software, but the adversary can easily bypass the verification by locating the hash value comparison instruction  ... 
doi:10.53555/nncse.v2i2.507 fatcat:jg6girddpvawzniepvwtwirpdq

Intellectual property protection for FPGA designs with soft physical hash functions: First experimental results

Stephanie Kerckhof, Francois Durvaux, Francois-Xavier Standaert, Benoit Gerard
2013 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)  
The use of Soft Physical Hash (SPH) functions has been recently introduced as a flexible and efficient way to detect Intellectual Property (IP) cores in microelectronic systems.  ...  Based on experiments, we put forward that SPH functions-based detection is a promising and low-cost solution for preventing anticounterfeiting, as it does not require any a-priori modification of the design  ...  François-Xavier Standaert is an Associate Researcher of the Belgian Fund for Scientific Research (FNRS-F.R.S.). Stéphanie Kerckhof is a PhD student funded by a FRIA grant, Belgium.  ... 
doi:10.1109/hst.2013.6581557 dblp:conf/host/KerckhofDSG13 fatcat:y7sl2zn3obfjrdnd6arpfjiuji

Survey of hardware protection of design data for integrated circuits and intellectual properties

Brice Colombier, Lilian Bossuet
2014 IET Computers & Digital Techniques  
This is now a critical issue for the microelectronics industry, mainly for fabless designers and intellectual properties designers.  ...  Over the past ten years, the designers of integrated circuits and intellectual properties have faced increasing threats including counterfeiting, reverse-engineering and theft.  ...  For this task, soft physical hash functions are particularly useful. They can also be found in the literature using the following search terms: robust hash functions or perceptual hash functions.  ... 
doi:10.1049/iet-cdt.2014.0028 fatcat:c2gzjh2mkbf7tjifyd44lrvrru

Technology Assessment: Exploring Possibilities to Encounter Problems Faced by Intellectual Property through Blockchain

M. Ismail, E. Grifell-Tatjé, A. Paz
2019 Zenodo  
Further it explores what makes blockchain suitable for intellectual property, the practical solutions available and the support different governments are offering.  ...  The extent and areas to which this technology can be of use are still being researched. This paper provides an in-depth review on the intellectual property and blockchain technology.  ...  Blockchain can be used as an open system or it can be a developed as a private and permissioned system for protection of intellectual assets.  ... 
doi:10.5281/zenodo.3300348 fatcat:ngnojtir45dtlfwgaznexbivby

Fragile IP Watermarking Techniques

Amr T. Abdel-Hamid, Sofiène Tahar
2008 2008 NASA/ESA Conference on Adaptive Hardware and Systems  
Intellectual property (IP) blocks reuse is essential for facilitating the design process of system-on-a-chip.  ...  The proposed technique protects hardware designs from alteration or any modifications that might occur to the design.  ...  Second, intellectual property protection applications, where the watermark is mainly used to convey the information about content ownership and intellectual property rights.  ... 
doi:10.1109/ahs.2008.73 dblp:conf/ahs/Abdel-HamidT08 fatcat:2h3kin2s45c7nooqnfulev26yi

Securing Soft IP Cores in FPGA based Reconfigurable Mobile Heterogeneous Systems [article]

Alberto Carelli, Cataldo Basile, Alessandro Savino, Alessandro Vallero, Stefano Di Carlo
2019 arXiv   pre-print
In particular, protecting the Intellectual Property of the exchanged soft IP cores is a serious concern.  ...  The available techniques for preserving integrity, confidentiality and authenticity suffer from the limitation of heavily relying onto the system designer.  ...  The hardware logic blocks implementing specific functions compose an Intellectual Property (IP) soft IP core.  ... 
arXiv:1912.00696v1 fatcat:hzog3clk7ngwvi73f4jj4djpry

A Chaotic IP Watermarking in Physical Layout Level Based on FPGA

W. Liang, X. Sun, Z. Xia, D. Sun, J. Long
2011 Radioengineering  
A new chaotic map based IP (Intellectual Property) watermarking scheme at physical design level is presented.  ...  A hashed chaotic sequence is used to scramble the watermark. Secondly, two pseudo-random sequences are generated by using chaotic maps.  ...  Meanwhile, in most of FPGA-based designs [1] , [2] , intellectual property (IP) reuse technology is widely used for shortening design cycle and reducing product risk.  ... 
doaj:826ff689fe1141f0b918de6f2b55c847 fatcat:xbqqxlyxuvfrvawcsc544d42qa

Robust FPGA intellectual property protection through multiple small watermarks

John Lach, William H. Mangione-Smith, Miodrag Potkonjak
1999 Proceedings of the 36th ACM/IEEE conference on Design automation conference - DAC '99  
A number of researchers have proposed using digital marks to provide ownership identification for intellectual property.  ...  The key technique involves using secure hash functions to generate and embed multiple small marks that are more detectable, verifiable, and secure than existing IP protection techniques.  ...  Reused modules include parameterized memory systems, I/O channels, ALUs, and complete processor cores. Design reuse has led to the rise of Intellectual Property Protection (IPP) concerns [8] .  ... 
doi:10.1145/309847.310080 dblp:conf/dac/LachMP99 fatcat:hfvlmewd4ngsrd2vnmx5bdhwze

Reconfigurable trusted computing in hardware

Thomas Eisenbarth, Tim Güneysu, Christof Paar, Ahmad-Reza Sadeghi, Dries Schellekens, Marko Wolf
2007 Proceedings of the 2007 ACM workshop on Scalable trusted computing - STC '07  
However, actual TPMs are mostly available for workstations and servers nowadays and rather for specific domain applications and not primarily for embedded systems.  ...  Our approach allows for (i) an efficient and scalable design and update of TPM functionalities, in particular for hardware-based crypto engines and accelerators, (ii) establishing a minimal trusted computing  ...  Based on the asymmetric means of an TCG-conform TPM, this can be used as an effective and flexible protection of Intellectual Property (IP) to provide device-specific application software.  ... 
doi:10.1145/1314354.1314360 dblp:conf/ccs/EisenbarthGPSSW07 fatcat:4fxicnybufgqrgssqdadd7ra2q

Aegis: A single-chip secure processor

G. Suh, Charles O'Donnell, Srinivas Devadas
2007 IEEE Design & Test of Computers  
To obtain a remote party's trust, computing systems must be able to guarantee the privacy of intellectual property and the integrity of program execution.  ...  This thesis also shows that using AEGIS requires only minor modifications to traditional operating systems and compilers.  ...  Also, because even the owner cannot compromise the system, AEGIS can provide strong Intellectual Property (IP) protection guarantees.  ... 
doi:10.1109/mdt.2007.4343587 fatcat:qzwlnqrklvat5kgjzia7yed47q

Hardware Signature Generation Using a Hybrid PUF and FSM Model for an SoC Architecture

Jagadeesh Kokila, Arjun Murali Das, Basha Shameedha Begum, Natarajan Ramasubramanian
2019 Periodica Polytechnica Electrical Engineering and Computer Science  
Major issues include hardware Trojan attack, hardware intellectual property (IP) theft, such as an illegal sale or use of firm intellectual property cores or integrated circuits (ICs) and physical attacks  ...  The results were obtained with the help of three Intellectual Property (IP) cores – Zedboard OLED IP, ISCAS'89 s1423 Benchmark IP and a Full Adder IP.  ...  Hence the development of an intellectual property protection (IPP) mechanisms is vital for the evolving reuse-based system design methodology.  ... 
doi:10.3311/ppee.13424 fatcat:gha4aoeqcbba3hxu7iwu6y3lmq

An Investigation Into Computer Forensic Tools

K. K. Arthur
2004 Information Security for South Africa  
In light of this, Computer Forensic Specialists employ state-of-the-art tools and methodologies in the extraction and analysis of data from storage devices used at the digital crime scene.  ...  This investigation will address commonalities across the Forensic tools, their essential differences and ultimately point out what features need to be improved in these tools to allow for effective autopsies  ...  The software then verifies the integrity of the image file and the original storage media using the MD5 hash function.  ... 
dblp:conf/issa/Arthur04 fatcat:siv47q3bd5dpti2lqug65hc3cq
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