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Grids, the TeraGrid and beyond

D.A. Reed
2003 Computer  
The two partnerships also include more than 60 geographically distributed academic and national laboratory partners. The TeraGrid project complements and builds upon the work of the two partnerships.  ...  The National Science Foundation PACI Program supports two partnerships: the National Computational Science Alliance (Alliance) and the National Partnership for Advanced Computational Infrastructure (NPACI  ...  Building the Next-Generation Itanium Processor • NCSA will house the largest of the TeraGrid computing systems.  ... 
doi:10.1109/mc.2003.1160057 fatcat:ecffqp46zbdzpjfdjna6wreazi

IT/Automation Cost Reduction in Intel's Manufacturing Environment

Brian Subirana
2003 Social Science Research Network  
Exhibit 11 shows a model of locally optimized computing groups versus centrally optimized and where Intel's factory computing groups were in 2002 on that scale.  ...  It has led to destructive competition in the industry where fares are now at five-year lows.''  ...  Appendix Relevant News Articles on Intel's Current and Future Business Prospects  ... 
doi:10.2139/ssrn.469282 fatcat:qmetfm7jxbaphojfeag4gjv5pa

EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes [article]

Pier Stanislao Paolucci, Iuliana Bacivarov, Devendra Rai, Lars Schor, Lothar Thiele, Hoeseok Yang, Elena Pastorelli, Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Francesco Simula (+2 others)
2014 arXiv   pre-print
The EURETILE project required the selection and coding of a set of dedicated benchmarks.  ...  This document is the first public deliverable of Work Package 7: Challenging Tiled Applications.  ...  )% Computation 7 See the notes to Project: EURETILE -European Reference Tiled Architecture Experiment Grant Agreement no.: 247846 Call: FP7-ICT-2009-4 Objective: FET -ICT-2009.8.1 Concurrent Tera-device  ... 
arXiv:1408.4587v1 fatcat:dl6xlqx7cba4hlvfqvhv6blavq

Front Matter

2021 2021 IEEE Microelectronics Design & Test Symposium (MDTS)  
The symposium provides a forum for discussions on the latest issues in the design and test of microelectronics, broadening our scope from previous years.  ...  Because of the Covid-19 pandemic, MDTS 2021 held its annual meeting online as five-hour live sessions over four consecutive days in May.  ...  Over the years, Igor has developed expertise in leading engineering groups in complex engineering projects (Nuclear and Aerospace).  ... 
doi:10.1109/mdts52103.2021.9476087 fatcat:niu4nujwobcfxnki6xfjdf7x34

Parallelism via Multithreaded and Multicore CPUs

A.C. Sodan, J. Machina, A. Deshmeh, K. Macnaughton, B. Esbaugh
2010 Computer  
Moore's Law, which projects that the density of circuits on chip will double every eighteen months, still applies and is providing hardware designers with the ability to add more complexity to a chip.  ...  However, only 25% of the additional chip space that became available per year was actually harvested by new architectural features. 2 Additionally, the performance gap between processors and memory limits  ...  This article has been accepted for publication in Computer but has not yet been fully edited. Some content may change prior to final publication.  ... 
doi:10.1109/mc.2010.75 fatcat:z34ptnd3rbgdvf7md5dmmqinfm

Fourth ACM SIGPLAN Workshop on Commercial Users of Functional Programming

Jeremy Gibbons
2007 Proceedings of the 4th ACM SIGPLAN workshop on Commercial users of functional programming - CUFP '07  
For the first time this year, the organisers had the encouraging dilemma of receiving more offers of presentations than would fit in the available time.  ...  The fourth workshop in the series took place in Freiburg, Germany on 4th October 2007, colocated as usual with the International Conference on Functional Programming.  ...  We needed something better for our next project!  ... 
doi:10.1145/1362702.1362703 fatcat:vizu5h47d5cglnms7s3v2scrpi

HPC Infrastructures Workshop #10

Huub Stoffers, Norbert Meyer, Gert Svensson, Andreas Johansson, Susanna Salminen, Hayk Shoukourian, François Robin
2019 Zenodo  
This paper summarises the presentations and discussions held at the workshop and identifies major trends in the field of the HPC centre infrastructures.  ...  The PRACE closed session, held at the end of the workshop, gathered attendees from PRACE Tier-0 and Tier-1 sites and gave the opportunity for exchanges between experts from the European supercomputing  ...  Acknowledgements This work was financially supported by the PRACE project funded in part by the EU's Horizon 2020 Research and Innovation programme (2014-2020) under grant agreement 730913.  ... 
doi:10.5281/zenodo.3773754 fatcat:dngi5432szcuvb4vm57ieqqywq

Internationalisation of R&D and Global Nature of Innovation: Emerging Trends in India

V. V. Krishna, S. K. Patra, S. Bhattacharya
2012 Science Technology & Society  
Further, the INSEAD Survey 2006 revealed that global firms would like to strengthen their 'optimally configured' R&D network over the next five years by opening up new R&D sites in China (22%), India (  ...  See, http://techresearch.intel.com/articles/Tera-Scale/1449.htm This chip has achieved a major technological challenge for Intel as it meets low power requirements of hand held devices and opens a new  ... 
doi:10.1177/097172181101700201 fatcat:5dj46jz27vdwdk72zimdpcogue

Reliability-Aware Quantization for Anti-Aging NPUs [article]

Sami Salamin, Georgios Zervakis, Ourania Spantidi, Iraklis Anagnostopoulos, Jörg Henkel, Hussam Amrouch
2021 arXiv   pre-print
Our evaluation, over ten state-of-the-art neural network architectures trained on the ImageNet dataset, demonstrates that for an entire lifetime of 10 years, the average accuracy loss is merely 3%.  ...  In this work, we are the first to propose a reliability-aware quantization to eliminate aging effects in NPUs while completely removing guardbands.  ...  This work is supported in part by the German Research Foundation (DFG) through the project "ACCROSS: Approximate Computing aCROss the System Stack".  ... 
arXiv:2103.04812v1 fatcat:3rfky7chebdqfgcfmiry4ny7i4

A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling

J Howard, S Dighe, S R Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, M Konow, M Riepen, M Gries, G Droege, T Lund-Larsen (+4 others)
2011 IEEE Journal of Solid-State Circuits  
At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W.  ...  Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores.  ...  In 2009, Greg became a part of the Microprocessor Research Lab within Intel Labs where he has since been designing and working on tera-and exa-scale research silicon and near threshold voltage computing  ... 
doi:10.1109/jssc.2010.2079450 fatcat:xljoxn6mizfivnresqkuyecpna

Eurolab-4-HPC Long-Term Vision on High-Performance Computing [article]

Theo Ungerer, Paul Carpenter
2018 arXiv   pre-print
Radical changes in computing are foreseen for the next decade.  ...  The US IEEE society wants to "reboot computing" and the HiPEAC Vision 2017 sees the time to "re-invent computing", both by challenging its basic assumptions.  ...  Intel's 5 nm production is targeted for early 2023, sources said, meaning its traditional 2-year process cadence is extending to roughly 2.5 to 3 years [5] .  ... 
arXiv:1807.04521v1 fatcat:5neetrgubjhnvcajcktpkohrzq

On whether and how D-RISC and Microgrids can be kept relevant (self-assessment report) [article]

Raphael Poss
2013 arXiv   pre-print
In the deconstruction phase, I review what I believe are the fundamental motivation and goals of the D-RISC/Microgrids enterprise, and identify what I judge are shortcomings: that the project did not deliver  ...  It reflects the opinions and insights that I have gained from working on this project during the period 2008-2013. This report is structed in two parts: deconstruction and reconstruction.  ...  years of silicon-technology scaling.  ... 
arXiv:1303.4892v1 fatcat:rlzlsdttxvenjoj3hk4gtmzof4

Hardware implementations of computer-generated holography: a review

Youchao Wang, Daoming Dong, Peter J. Christopher, Andrew Kadis, Ralf Mouthaan, Fan Yang, Timothy D. Wilkinson
2020 Optical Engineering: The Journal of SPIE  
One of the major issues related to computer hologram generation is the massive computational power required. Hardware accelerators are used to accelerate this process.  ...  Computer-generated holography (CGH) is a technique to generate holographic interference patterns.  ...  The first four generations of HORN use DSP or small-scale FPGA chips for real-time computation tasks. 86, [104] [105] [106] The later four generations of devices consist of large-scale FPGA chips embedded  ... 
doi:10.1117/1.oe.59.10.102413 fatcat:2az3fb5k6ngstdi5razgtkuh5q

Scalable, parallel computers: Alternatives, issues, and challenges

Gordon Bell
1994 International journal of parallel programming  
Program or problem scalability, first observed by Gustafson et is a property of a program/machine combination that determines the ability of a problem to operate at various scales (sizes) on a given scale  ...  The 1990s will be the era of scalable computers. By giving up uniform memory access, computers can be built that scale over a range of several thousand.  ...  The projection (Bell''*') that microprocessors would improve at a 60% per year rate following Moore's Law, providing a quadrupling of performance each three years, still appears to be possible (Bell'')  ... 
doi:10.1007/bf02577791 fatcat:jnvgpsftabcnnabkmpcm5kifqq

Fast ray tracing and the potential effects on graphics and gaming courses

Peter Shirley, Kelvin Sung, Erik Brunvand, Alan Davis, Steven Parker, Solomon Boulos
2008 Computers & graphics  
The modern graphics processing units (GPUs), found on almost every personal computer, use the z-buffer algorithm to compute visibility.  ...  Since computer gaming is one of the most important industry driving graphics hardware and the fact that recently there are many computer science courses related to games and games development, we also  ...  All opinions, findings, conclusions, and recommendations in this work are those of the authors and do not necessarily reflect the views of the National Science Foundation or Microsoft.  ... 
doi:10.1016/j.cag.2008.01.007 fatcat:wpfikfvnjfcdxea7ombcvytn64
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